| | Annual ACM IEEE Design Automation Conference archiveProceedings of the 38th annual Design Automation Conference 2001, Las Vegas, Nevada, United States | | | Table of Contents | | | | The electronics industry supply chain (panel session): who does what?
Rita Glover, Marc Halpern, Rick Becks, Richard Kubin, Henry Jurgens, Rich Cassidy, Ted Vucurevich
Pages: 1 - 2
Full text available:  Pdf(116 KB) | | | | Future performance challenges in nanometer design
Dennis Sylvester, Himanshu Kaul
Pages: 3 - 8
Full text available: Pdf(253 KB) | | | | IC design in high-cost nanometer-technologies era
Wojciech Maly
Pages: 9 - 14
Full text available: Pdf(240 KB) | | | | LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana
Pages: 15 - 20
Full text available: Pdf(347 KB) | | | | Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
Tiberiu Chelcea, Steven M. Nowick
Pages: 21 - 26
Full text available: Pdf(124 KB) | | | | Latency-driven design of multi-purpose systems-on-chip
Seapahn Maguerdichian, Milenko Drinic, Darko Kirovski
Pages: 27 - 30 | | | | Estimation of speed, area, and power of parameterizable, soft IP
Jagesh Sanghavi, Albert Wang
Pages: 31 - 34
Full text available: Pdf(71 KB) | | | | Formal property verification by abstraction refinement with formal, simulation and hybrid engines
Dong Wang, Pei-Hsin Jiang, James Kukula, Yunshan Zhu, Tony Ma, Robert Damiano
Pages: 35 - 40
Full text available: Pdf(179 KB) | | | | Scalable hybrid verification of complex microprocessors
Maher Mneimneh, Fadi Aloul, Chris Weaver, Saugata Chatterjee, Karem Sakallah, Todd Austin
Pages: 41 - 46
Full text available: Pdf(150 KB) | | | | Symbolic RTL simulation
Alferd Kölbl, James Kukula, Robert Damiano
Pages: 47 - 52 | | | | A unified DFT architecture for use with IEEE 1149.1 and VSIA/IEEE P1500 compliant test access controllers
Bulent I. Dervisoglu
Pages: 53 - 58
Full text available: Pdf(199 KB) | | | | Instruction-level DFT for testing processor and IP cores in system-on-a-chip
Wei-Cheng Lai, Kwang-Ting Cheng
Pages: 59 - 64
Full text available: Pdf(75 KB) | | | | Test strategies for BIST at the algorithmic and register-transfer levels
Kelly A. Ockunzzi, Chris Papachristou
Pages: 65 - 70
Full text available: Pdf(131 KB) | | | | The next HDL (panel session): if C++ is ;the answer, what was the question?
Rajesh Gupta, Gerard Berry, Ramesh Chandra, Daniel Gajski, Kris Konigsfeld, Patrick Schaumont, Ingrid Verbauhede
Pages: 71 - 72
Full text available: Pdf(118 KB) | | | | Reticle enhancement technology: implications and challenges for physical design
W. Grobman, M. Thompson, R. Wang, C. Yuan, R. Tian, E. Demircan
Pages: 73 - 78
Full text available: Pdf(228 KB) | | | | Enabling alternating phase shifted mask designs for a full logic gate level: design rules and design rule checking
Lars Liebmann
Pages: 79 - 84
Full text available: Pdf(80 KB) | | | | Layout design methodolgies for sub-wavelength manufacturing
Michael L. Rieger, Jeffrey P. Mayhew, Sridhar Panchapakesan
Pages: 85 - 88
Full text available: Pdf(705 KB) | | | | Adoption of OPC and the impact on design and layout
F. M. Schellenberg, Olivier Toublan, Luigi Capodieci, Bob Socha
Pages: 89 - 92 | | | | Adoption of OPC and the impact on design and layout
F. M. Schellenberg, Olivier Toublan, Luigi Capodieci, Bob Socha
Pages: 89 - 92
Full text available: Pdf(575 KB) | | | | Practical application of full-feature alternating phase-shifting technology for a phase-aware standard-cell design flow
Michael Sanie, Michel Côté, Philippe Hurat, Vinod Malhotra
Pages: 93 - 96
Full text available: Pdf(1.30 MB) | | | | Practical application of full-feature alternating phase-shifting technology for a phase-aware standard-cell design flow
Michael Sanie, Michel Côté, Philippe Hurat, Vinod Malhotra
Pages: 93 - 96 | | | | Layout-driven hot-carrier degradation minimization using logic restructuring techniques
Chih-Wei Chang, Kai Wang, Malgorzata Marek-Sadowska
Pages: 97 - 102
Full text available: Pdf(153 KB) | | | | An algorithm for bi-decomposition of logic functions
Alan Mishchenko, Bernd Steinbach, Marek Perkowski
Pages: 103 - 108
Full text available: Pdf(251 KB) | | | | Factoring and recognition of read-once functions using cographs and normality
Martin C. Golumbic, Aviad Mintz, Udi Rotics
Pages: 109 - 114
Full text available: Pdf(243 KB) | | | | Logic minimization using exclusive OR gates
Valentina Ciriani
Pages: 115 - 120
Full text available: Pdf(263 KB) | | | | Design of half-rate clock and data recovery circuits for optical communication systems
Jafar Savoj, Behzad Razavi
Pages: 121 - 126
Full text available: Pdf(1.78 MB) | | | | A novel method for stochastic nonlinearity analysis of a CMOS pipeline ADC
David Goren, Eliyahu Shamsaevc, A. Wagner
Pages: 127 - 132
Full text available: Pdf(334 KB) | | | | Behavioral partitioning in the synthesis of mixed analog-digital systems
Sree Ganesan, Ranga Vemuri
Pages: 133 - 138
Full text available: Pdf(153 KB) | | | | Efficient DDD-based symbolic analysis of large linear analog circuits
Wim Verhaegen, Georges Gielen
Pages: 139 - 144
Full text available: Pdf(89 KB) | | | | Random limited-scan to improve random pattern testing of scan circuits
Irith Pomeranz
Pages: 145 - 150
Full text available: Pdf(77 KB) | | | | Test volume and application time reduction through scan chain concealment
Ismet Bayraktaroglu, Alex Orailoglu
Pages: 151 - 155
Full text available: Pdf(78 KB) | | | | An approach to test compaction for scan circuits that enhances at-speed testing
Irith Pomeranz, Sudhakar Reddy
Pages: 156 - 161
Full text available: Pdf(87 KB) | | | | Generating efficient tests for continuous scan
Sying-Jyan Wang, Sheng-Nan Chiou
Pages: 162 - 165
Full text available: Pdf(151 KB) | | | | Combining low-power scan testing and test data compression for system-on-a-chip
Anshuman Chandra, Krishnendu Chakrabarty
Pages: 166 - 169
Full text available: Pdf(197 KB) | | | | Your core— my problem? (panel session): integration and verification of IP
Gabe Moretti, Tom Anderson, Janick Bergeron, Ashish Dixit, Peter Flake, Tim Hopes, Ramesh Narayanaswamy
Pages: 170 - 171
Full text available: Pdf(129 KB) | | | | A quick safari through the reconfiguration jungle
Patrick Schaumont, Ingrid Verbauwhede, Kurt Keutzer, Majid Sarrafzadeh
Pages: 172 - 177
Full text available: Pdf(269 KB) | | | | Re-configurable computing in wireless
Bill Salefski, Levent Caglar
Pages: 178 - 183
Full text available: Pdf(241 KB) | | | | Hardware/software instruction set configurability for system-on-chip processors
Albert Wang, Earl Killian, Dror Maydan, Chris Rowen
Pages: 184 - 188
Full text available: Pdf(156 KB) | | | | A practical methodology for early buffer and wire resource allocation
Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia
Pages: 189 - 194
Full text available: Pdf(166 KB) | | | | Creating and exploiting flexibility in steiner trees
Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh
Pages: 195 - 198
Full text available: Pdf(162 KB) | | | | Simultaneous shield insertion and net ordering under explicit RLC noise constraint
Kevin M. Lepak, Irwan Luwandi, Lei He
Pages: 199 - 202
Full text available: Pdf(152 KB) | | | | On optimum switch box designs for 2-D FPGAs
Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung
Pages: 203 - 208
Full text available: Pdf(828 KB) | | | | Dependency preserving probabilistic modeling of switching activity using bayesian networks
Sanjukta Bhanja, N. Ranganathan
Pages: 209 - 214
Full text available: Pdf(226 KB) | | | | A static estimation technique of power sensitivity in logic circuits
Taewhan Kim, Ki-Seok Chung, C. L. Liu
Pages: 215 - 219
Full text available: Pdf(202 KB) | | | | JouleTrack: a web based tool for software energy profiling
Amit Sinha, Anantha P. Chandrakasan
Pages: 220 - 225
Full text available: Pdf(209 KB) | | | | Effective use of boolean satisfiability procedures in the formal verification of superscalar and VLIW
Miroslav N. Velev, Randal E. Bryant
Pages: 226 - 231
Full text available: Pdf(103 KB) | | | | Circuit-based Boolean Reasoning
Andreas Kuehlmann, Malay K. Ganai, Viresh Paruthi
Pages: 232 - 237
Full text available: Pdf(146 KB) | | | | Checking equivalence for partial implementations
Christoph Scholl, Bernd Becker
Pages: 238 - 243
Full text available: Pdf(114 KB) | | | | Validating the intel pentium 4 microprocessor
Bob Bentley
Pages: 244 - 248
Full text available: Pdf(164 KB) | | | | Nuts and bolts of core and SoC verification
Ken Albin
Pages: 249 - 252
Full text available: Pdf(164 KB) | | | | Teaching future verification engineers: the forgotten side of logic design
Fusun Ozguner, Duane Marhefka, Joanne DeGroat, Bruce Wile, Jennifer Stofer, Lyle Hanrahan
Pages: 253 - 255
Full text available: Pdf(115 KB) | | | | SoC integration of reusable baseband bluetooth IP
Torbjörn Grahm, Barry Clark
Pages: 256 - 231 | | | | One-chip bluetooth Asic challenges
Paul T. M. van Zeijl
Page: 262
Full text available: Pdf(79 KB) | | | | Transformations for the synthesis and optimization of asynchronous distributed control
Michael Theobald, Steven M. Nowick
Pages: 263 - 268
Full text available: Pdf(166 KB) | | | | Speculation techniques for high level synthesis of control intensive designs
Sumit Gupta, Nick Savoiu, Sunwoo Kim, Nikil Dutt, Rajesh Gupta, Alex Nicolau
Pages: 269 - 272
Full text available: Pdf(135 KB) | | | | Parallelizing DSP nested loops on reconfigurable architectures using data context switching
Kiran Bondalapati
Pages: 273 - 276
Full text available: Pdf(123 KB) | | | | Using symbolic algebra in algorithmic level DSP synthesis
Armita Peymandoust, Giovanni De Micheli
Pages: 277 - 282
Full text available: Pdf(87 KB) | | | | Computing logic-stage delays using circuit simulation and symbolic elmore analysis
Clayton B. McDonald, Randal E. Bryant
Pages: 283 - 288
Full text available: Pdf(118 KB) | | | | A new gate delay model for simultaneous switching and its applications
Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
Pages: 289 - 294
Full text available: Pdf(163 KB) | | | | Static timing analysis including power supply noise effect on propagation delay in VLSI circuits
Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
Pages: 295 - 300
Full text available: Pdf(242 KB) | | | | Simulation-based test algorithm generation and port scheduling for multi-port memories
Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu
Pages: 301 - 306
Full text available: Pdf(151 KB) | | | | Improving bus test via IDDT and boundary scan
Shih-Yu Yang, Christos A. Papachristou, Massood Tabib-Azar
Pages: 307 - 312
Full text available: Pdf(262 KB) | | | | Fault characterizations and design-for-testability technique for detecting $I_{DDQ}$ faults in CMOS/BiCMOS circuits
Kaamran Raahemifar, Majid Ahmadi
Pages: 313 - 316
Full text available: Pdf(152 KB) | | | | Testing for interconnect crosstalk defects using on-chip embedded processor cores
Li Chen, Xiaoliang Bai, Sujit Dey
Pages: 317 - 320
Full text available: Pdf(70 KB) | | | | (When) will FPGAs kill ASICs? (panel session)
Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen
Pages: 321 - 322
Full text available: Pdf(125 KB) | | | | Inductance 101: modeling and extraction
Michael W. Beattie, Lawrence T. Pileggi
Pages: 323 - 328
Full text available: Pdf(613 KB) | | | | Inductance 101: analysis and design issues
Kaushik Gala, David Blaauw, Junfeng Wang, Vladimir Zolotov, Min Zhao
Pages: 329 - 334
Full text available: Pdf(204 KB) | | | | Modeling magnetic coupling for on-chip interconnect
Michael W. Beattie, Lawrence T. Pileggi
Pages: 335 - 340
Full text available: Pdf(287 KB) | | | | Min/max on-chip inductance models and delay metrics
Yi-Chang Lu, Mustafa Celik, Tak Young, Lawrence T. Pileggi
Pages: 341 - 346
Full text available: Pdf(149 KB) | | | | Utilizing memory bandwidth in DSP embedded processors
Catherine H. Gebotys
Pages: 347 - 352 | | | | Address code generation for digital signal processors
Sathishkumar Udayanarayanan, Chaitali Chakrabarti
Pages: 353 - 358
Full text available: Pdf(172 KB) | | | | Reducing memory requirements of nested loops for embedded systems
J. Ramanujam, Jinpyo Hong, Mahmut Kandemir, A. Narayan
Pages: 359 - 364
Full text available: Pdf(174 KB) | | | | Detection of partially simultaneously alive signals in storage requirement estimation for data intensive applications
PerGunnar Kjeldsberg, Francky Catthoor, Einar J. Aas
Pages: 365 - 370
Full text available: Pdf(279 KB) | | | | A new structural pattern matching algorithm for technology mapping
Min Zhao, Sachin S. Sapatnekar
Pages: 371 - 376
Full text available: Pdf(232 KB) | | | | Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect
Srirang K. Karandikar, S. Sapatnekar
Pages: 377 - 382
Full text available: Pdf(115 KB) | | | | Latency and latch count minimization in wave steered circuits
Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska
Pages: 383 - 388
Full text available: Pdf(152 KB) | | | | Performance-driven multi-level clustering with application to hierarchical FPGA mapping
Jason Cong, Michail Romesis
Pages: 389 - 394
Full text available: Pdf(217 KB) | | | | Application of constraint-based heuristics in collaborative design
Juan Antonio Carballo, Stephen W. Director
Pages: 395 - 400
Full text available: Pdf(416 KB) | | | | A universal client for distributed networked design and computing
Franc Brglez, Hemang Lavana
Pages: 401 - 406
Full text available: Pdf(206 KB) | | | | Hypermedia-aided design
Darko Kirovski, Milenko Drinic, Miodrag Potkonjak
Pages: 407 - 412
Full text available: Pdf(595 KB) | | | | A framework for object oriented hardware specification, verification, and synthesis
T. Kuhn, T. Oppold, M. Winterholer, W. Rosenstiel, Marc Edwards, Yaron Kashai
Pages: 413 - 418
Full text available: Pdf(222 KB) | | | | When will the analog design flow catch up with digital methodology? (panel session)
Georges Gielen, Mar Hershenson, Ken Kundert, Philippe Magarshack, Akira Matsuzawa, Ronald A. Rohrer, Ping Yang
Page: 419
Full text available: Pdf(116 KB) | | | | Achieving 550 MHz in an ASIC methodology
D. G. Chinnery, B. Nikolic, K. Keutzer
Pages: 420 - 425
Full text available: Pdf(1.21 MB) | | | | A semi-custom design flow in high-performance microprocessor design
Gregory A. Northrop, Pong-Fei Lu
Pages: 426 - 431
Full text available: Pdf(187 KB) | | | | Reducing the frequency gap between ASIC and custom designs: a custom perspective
Stephen E. Rich, Matthew J. Parker, Jim Schwartz
Pages: 432 - 437
Full text available: Pdf(220 KB) | | | | Low-energy intra-task voltage scheduling using static timing analysis
Dongkun Shin, Jihong Kim, Seongsoo Lee
Pages: 438 - 443
Full text available: Pdf(113 KB) | | | | Battery-aware static scheduling for distributed real-time embedded systems
Jiong Luo, Niraj K. Jha
Pages: 444 - 449
Full text available: Pdf(239 KB) | | | | An approach to incremental design of distributed embedded systems
Paul Pop, Petru Eles, Traian Pop, Zebo Peng
Pages: 450 - 455
Full text available: Pdf(111 KB) | | | | Signal representation guided synthesis using carry-save adders for synchronous data-path circuits
Zhan Yu, Meng-Lin Yu, Alan N. Willson, Jr.
Pages: 456 - 461
Full text available: Pdf(103 KB) | | | | Improved merging of datapath operators using information content and required precision analysis
Anmol Mathur, Sanjeev Saluja
Pages: 462 - 467
Full text available: Pdf(218 KB) | | | | Digital filter synthesis based on minimal signed digit representation
In-Cheol Park, Hyeong-Ju Kang
Pages: 468 - 473
Full text available: Pdf(226 KB) | | | | Publicly detectable techniques for the protection virtual components
Gang Qu
Pages: 474 - 479
Full text available: Pdf(132 KB) | | | | Watermarking of SAT using combinatorial isolation lemmas
Rupak Majumdar, Jennifer L. Wong
Pages: 480 - 485
Full text available: Pdf(92 KB) | | | | Watermarking graph partitioning solutions
Greg Wolfe, Jennifer L. Wong, Miodrag Potkonjak
Pages: 486 - 489
Full text available: Pdf(86 KB) | | | | Hardware metering
Farinaz Koushanfar, Gang Qu
Pages: 490 - 493
Full text available: Pdf(199 KB) | | | | Technical visualizations in VLSI design: visualization
Phillip J. Restle
Pages: 494 - 499
Full text available: Pdf(812 KB) | | | | Using texture mapping with mipmapping to render a VLSI layout
Jeff Solomon, Mark Horowitz
Pages: 500 - 505
Full text available: Pdf(708 KB) | | | | Web-based algorithm animation
Marc Najork
Pages: 506 - 511
Full text available: Pdf(264 KB) | | | | Speeding up control-dominated applications through microarchitectural customizations in embedded processors
Peter Petrov, Alex Orailoglu
Pages: 512 - 517
Full text available: Pdf(86 KB) | | | | Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip
Damien Lyonnard, Sungjoo Yoo, Amer Baghdadi, Ahmed A. Jerraya
Pages: 518 - 523
Full text available: Pdf(285 KB) | | | | Dynamic voltage scaling and power management for portable systems
Tajana Simunic, Luca Benini, Andrea Acquaviva, Peter Glynn, Giovanni De Micheli
Pages: 524 - 529
Full text available: Pdf(248 KB) | | | | Chaff: engineering an efficient SAT solver
Matthew W. Moskewicz, Conor F. Madigan, Ying Zhao, Lintao Zhang, Sharad Malik
Pages: 530 - 535
Full text available: Pdf(196 KB) | | | | Dynamic detection and removal of inactive clauses in SAT with application in image computation
Aarti Gupta, Anubhav Gupta, Zijiang Yang, Pranav Ashar
Pages: 536 - 541
Full text available: Pdf(192 KB) | | | | SATIRE: a new incremental satisfiability engine
Jesse Whittemore, Joonyoung Kim, Karem Sakallah
Pages: 542 - 545
Full text available: Pdf(109 KB) | | | | A framework for low complexitgy static learning
Emil Gizdarski, Hideo Fujiwara
Pages: 546 - 549
Full text available: Pdf(173 KB) | | | | Fast power/ground network optimization based on equivalent circuit modeling
X.-D. Sheldon Tan, C.-J. Richard Shi
Pages: 550 - 554
Full text available: Pdf(188 KB) | | | | An interconnect energy model considering coupling effects
Taku Uchino, Jason Cong
Pages: 555 - 558
Full text available: Pdf(168 KB) | | | | Efficient large-scale power grid analysis based on preconditioned krylov-subspace iterative methods
Tsung-Hao Chen, Charlie Chung-Ping Chen
Pages: 559 - 562
Full text available: Pdf(274 KB) | | | | Using conduction modes basis functions for efficient electromagnetic anaysis of on-chip and off-chip interconnect
Luca Daniel, Alberto Sangiovanni, Jacob White
Pages: 563 - 566
Full text available: Pdf(158 KB) | | | | Analysis of non-uniform temperature-dependent interconnect performance in high performance ICs
Amir H. Ajami, Kaustav Banerjee, Massoud Pedram, Lukas P. P. P. van Ginneken
Pages: 567 - 572
Full text available: Pdf(294 KB) | | | | VHDL-based design and design methodology for reusable high performance direct digital requency synthesizers
Ireneusz Janiszewski, Bernhard Hoppe, Hermann Meuth
Pages: 573 - 578
Full text available: Pdf(226 KB) | | | | Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit symmetric block ciphers
Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim
Pages: 579 - 584
Full text available: Pdf(260 KB) | | | | MetaCores: design and optimization techniques
Seapahn Meguerdichian, Farinaz Koushanfar, Advait Morge, Dusan Petranovic, Miodrag Potkonjak
Pages: 585 - 590
Full text available: Pdf(284 KB) | | | | Is nanometer design under control? (panel session)
Andrew B. Kahng, Nancy Nettleton, John Cohn, Shekhar Borkar, Louis Scheffer, Ed Cheng, Sang Wang
Pages: 591 - 592
Full text available: Pdf(106 KB) | | | | A hardware/software co-design flow and IP library based on simulink
L. M. Reyneri, F. Cucinotta, A. Serra, L. Lavagno
Pages: 593 - 598
Full text available: Pdf(120 KB) | | | | System-level power/performance analysis for embedded systems design
Amit Nandi, Radu Marculescu
Pages: 599 - 604
Full text available: Pdf(207 KB) | | | | High-level software energy macro-modeling
T. K. Tan, A. K. Raghunathan, G. Lakishminarayana, N. K. Jha
Pages: 605 - 610
Full text available: Pdf(206 KB) | | | | Model checking of S3C2400X industrial embedded SOC product
Hoon Choi, Byeongwhee Yun, Yuntae Lee, Hyunglae Roh
Pages: 611 - 616
Full text available: Pdf(759 KB) | | | | Semi-formal test generation with genevieve
Julia Dushina, Mike Benjamin, Daniel Geist
Pages: 617 - 622
Full text available: Pdf(147 KB) | | | | A transaction-based unified simulation/emulation architecture for functional verification
Murali Kudlugi, Soha Hassoun, Charles Selvidge, Duaine Pryor
Pages: 623 - 628
Full text available: Pdf(201 KB) | | | | Integrated high-level synthesis and power-net routing for digital design under switching noise constraints
Alex Doboli, Ranga Vemuri
Pages: 629 - 634
Full text available: Pdf(235 KB) | | | | Integrating scheduling and physical design into a coherent compilation cycle for reconfigurable computing architectures
Kia Bazargan, Seda Ogrenci, Majid Sarrafzadeh
Pages: 635 - 640
Full text available: Pdf(231 KB) | | | | Statistical design space exploration for application-specific unit synthesis
Davide Bruni, Alessandro Bogliolo, Luca Benini
Pages: 641 - 646
Full text available: Pdf(179 KB) | | | | Static schedluing of multiple asynchronous domains for functional verification
Murali Kudlugi, Charles Selvidge, Russell Tessier
Pages: 647 - 652
Full text available: Pdf(100 KB) | | | | Functional correlation analysis in crosstalk induced critical paths identification
Tong Xiao, Malgorzata Marek-Sadowska
Pages: 653 - 656
Full text available: Pdf(60 KB) | | | | An advanced timing characterization method using mode dependecy
Hakan Yalcin, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji, Karem Sakallah, John Hayes
Pages: 657 - 660
Full text available: Pdf(72 KB) | | | | Fast statistical timing analysis by probabilistic event propagation
Jing-Jia Liou, Kwang-Ting Cheng, Sandip Kundu, Angela Krstic
Pages: 661 - 666
Full text available: Pdf(98 KB) | | | | Addressing the system-on-a-chip interconnect woes through communication-based design
M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, S. Malik, J. Rabaey, A. Sangiovanni-Vencentelli
Pages: 667 - 672
Full text available: Pdf(180 KB) | | | | Micronetwork-based integration for SOCs: 673
Drew Wingard
Page: 677 | | | | On-chip communication architecture for OC-768 network processors
Faraydon Karim, Anh Nguyen, Sujit Dey, Ramesh Rao
Pages: 678 - 683
Full text available: Pdf(245 KB) | | | | Route packets, not wires: on-chip inteconnection networks
William J. Dally, Brian Towles
Pages: 684 - 689
Full text available: Pdf(125 KB) | | | | Dynamic management of scratch-pad memory space
M. Kandemir, J. Ramanujam, J. Irwin, N. Vijaykrishnan, I. Kadayif, A. Parikh
Pages: 690 - 695
Full text available: Pdf(257 KB) | | | | Clustered VLIW architecture with predicated switching
Margarida F. Jacome, Gustavo de Veciana, Satish Pillai
Pages: 696 - 701
Full text available: Pdf(190 KB) | | | | High-quality operation binding for clustered VLIW datapaths
Viktor S. Lapinskii, Margarida F. Jacome, Gustavo A. de Veciana
Pages: 702 - 707
Full text available: Pdf(127 KB) | | | | Fast bit-true simulation
Holger Keding, Martin Coors, Olaf Lüthje, Heinrich Meyr
Pages: 708 - 713
Full text available: Pdf(303 KB) | | | | Timing analysis with crosstalk as fixpoints on complete lattice
Hai Zhou, Narendra Shenoy, William Nicholls
Pages: 714 - 719
Full text available: Pdf(231 KB) | | | | Driver modeling and alignment for worst-case delay noise
Supamas Sirichotiyakul, David Blaauw, Chanhee Oh, Rafi Levy, Vladimir Zolotov, Jingyan Zuo
Pages: 720 - 725
Full text available: Pdf(895 KB) | | | | False coupling interactions in static timing analysis
Ravishankar Arunachalam, Ronald D. Blanton, Lawrence T. Pileggi
Pages: 726 - 731
Full text available: Pdf(156 KB) | | | | Coupling delay optimization by temporal decorrelation using dual threshold voltage technique
Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang
Pages: 732 - 737
Full text available: Pdf(110 KB) | | | | Input space adaptive design: a high-level methodology for energy and performance optimization
Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
Pages: 738 - 743
Full text available: Pdf(265 KB) | | | | A$^{\mbox{\huge\bf 2}}$BC: adaptive address bus coding for low power deep sub-micron designs
Jörg Henkel, Haris Lekatsas
Pages: 744 - 749
Full text available: Pdf(945 KB) | | | | Coupling-driven bus design for low-power application-specific systems
Youngsoo Shin, Takayasu Sakurai
Pages: 750 - 753
Full text available: Pdf(95 KB) | | | | Modeling and minimization of interconnect energy dissipation in nanometer technologies
Clark N. Taylor, Sujit Dey, Yi Zhao
Pages: 754 - 757
Full text available: Pdf(76 KB) | | | | A true single-phase 8-bit adiabatic multiplier
Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou
Pages: 758 - 763
Full text available: Pdf(648 KB) | | | | TCG: a transitive closure graph-based representation for non-slicing floorplans
Jai-Ming Lin, Yao-Wen Chang
Pages: 764 - 769
Full text available: Pdf(142 KB) | | | | Floorplanning with abutment constraints and L-shpaed/T-shaped blocks baed on corner block list
Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
Pages: 770 - 775
Full text available: Pdf(263 KB) | | | | Improved cut sequences for partitioning based placement
Mehmet Can Yildiz, Patrick H. Madden
Pages: 776 - 779
Full text available: Pdf(47 KB) | | | | Timing driven placement using physical net constraints
Bill Halpin, C. Y. Roger Chen, Naresh Sehgal
Pages: 780 - 783
Full text available: Pdf(185 KB) | | | | From architecture to layout: partitioned memory synthesis for embedded systems-on-chip
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Full text available: Pdf(125 KB) | | | | Built-in self-test for signal integrity
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Pages: 834 - 839 | | | | Power-aware scheduling under timing constraints for mission-critical embedded systems
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Pages: 840 - 845
Full text available: Pdf(119 KB) | | | | Exploring SOI device structures and interconnect architecures for 3-dimensional integration
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Full text available: Pdf(343 KB) | | | | Two-dimensional position deteciton system with MEMS accelerometer for MOUSE applications
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Full text available: Pdf(1.40 MB) | | | | Mismatch analysis and direct yield optimization by specwise linearization and feasibility-guided search
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Full text available: Pdf(187 KB) | |
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