| | International Symposium on Computer Architecture archive25 years of the international symposia on Computer architecture (selected papers) 1998, Barcelona, Spain June 27 - July 02, 1998 | | | Table of Contents | | | | Retrospective: Banyan networks for partitioning multiprocessor systems
Jack Lipovski
Page: 1
Full text available:  Pdf(39 KB) | | | | Retrospective: a preliminary architecture for a basic data flow processor
Jack B. Dennis
Pages: 2 - 4
Full text available: Pdf(338 KB) | | | | Retrospective: improving the throughput of a pipeline by insertion of delays
Janak H. Patel
Page: 5
Full text available: Pdf(118 KB) | | | | Retrospective: what have we learned from the PDP-11—what we have learned from VAX and Alpha
Gorden Bell, W. D. Strecker
Pages: 6 - 10
Full text available: Pdf(666 KB) | | | | Retrospective: an instruction timing model of CPU performance
Leonard J. Shustek, Bernard L. Peuto
Pages: 11 - 12
Full text available: Pdf(226 KB) | | | | Retrospective: a retrospective on high-level language computer architecture
David R. Ditzel, David A. Patterson
Pages: 13 - 14
Full text available: Pdf(226 KB) | | | | Retrospective: architecture of a massively parallel processor
Ken Batcher
Pages: 15 - 16
Full text available: Pdf(152 KB) | | | | Retrospective: a processor for a high-performance personal computer
Ken Pier
Pages: 17 - 19
Full text available: Pdf(364 KB) | | | | Retrospective: lockup-free instruction fetch/prefetch cache organization
David Kroft
Pages: 20 - 21
Full text available: Pdf(208 KB) | | | | Retrospective: a study of branch prediction strategies
James E. Smith
Pages: 22 - 23
Full text available: Pdf(211 KB) | | | | Retrospective: RISC I: a reduced instruction set computer
David A. Patterson, Carlo H. Séquin
Pages: 24 - 26
Full text available: Pdf(385 KB) | | | | Retrospective: decoupled access/execute architectures
James E. Smith
Pages: 27 - 28
Full text available: Pdf(175 KB) | | | | Retrospective: a personal retrospective on the NYU ultracomputer
Allan Gottlieb
Pages: 29 - 31
Full text available: Pdf(402 KB) | | | | Retrospective: using cache memory to reduce processor-memory traffic
James R. Goodman
Pages: 32 - 33
Full text available: Pdf(236 KB) | | | | Retrospective: very long instruction word architectures and the ELI-512
Joseph A. Fisher
Pages: 34 - 36
Full text available: Pdf(343 KB) | | | | Retrospective: characterization of processor performance in the VAX-11/780
Joel S. Emer, Douglas W. Clark
Pages: 37 - 38
Full text available: Pdf(257 KB) | | | | Retrospective: a low-overhead coherence solution for multiprocessors with private cache memories
Janak H. Patel
Pages: 39 - 41
Full text available: Pdf(310 KB) | | | | Retrospective: implementing precise interrupts in pipelined processors
James E. Smith
Page: 42
Full text available: Pdf(118 KB) | | | | Retrospective: HPSm, a high performance restricted data flow architecture having minimal functionality
Wen-mei W. Hwu, Yale N. Patt
Pages: 43 - 44
Full text available: Pdf(190 KB) | | | | Retrospective: a retrospective on the Warp machines
Thomas Gross, Monica Lam
Pages: 45 - 47
Full text available: Pdf(399 KB) | | | | Retrospective: memory access buffering in multiprocessors
Michel Dubois, Christoph Scheurich
Pages: 48 - 50
Full text available: Pdf(392 KB) | | | | Retrospective: instruction issue logic for high-performance, interruptable pipelined processors
Gurindar S. Sohi
Pages: 51 - 53
Full text available: Pdf(343 KB) | | | | Retrospective: the J-machine
William J. Dally, Andrew Chien, Stuart Fiske, Waldemar Horwat, Richard Lethin, Michael Noakes, Peter Nuth, Ellen Spertus, Deborah Wallach, D. Scott Wills, Andrew Chang, John Keen
Pages: 54 - 58
Full text available: Pdf(605 KB) | | | | Retrospective: on the inclusion properties for multi-level cache hierarchies
Jean-Loup Baer, Wen-Hann Wang
Pages: 59 - 60
Full text available: Pdf(199 KB) | | | | Retrospective: evaluation of directory schemes for cache coherence
John Hennessy
Pages: 61 - 62
Full text available: Pdf(239 KB) | | | | Retrospective: weak ordering—a new definition
Sarita V. Adve, Mark D. Hill
Pages: 63 - 66
Full text available: Pdf(431 KB) | | | | Retrospective: memory consistency and event ordering in scalable shared-memory multiprocessors
Kourosh Gharachorloo
Pages: 67 - 70
Full text available: Pdf(537 KB) | | | | Retrospective: improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
Norman P. Jouppi
Pages: 71 - 73
Full text available: Pdf(298 KB) | | | | Retrospective: Monsoon: an explicit token-store architecture
George M. Papadopoulos, David E. Culler
Pages: 74 - 76
Full text available: Pdf(392 KB) | | | | Retrospective: IMPACT: an architectural framework for multiple-instruction issue
Wen-mei W. Hwu
Pages: 77 - 79
Full text available: Pdf(326 KB) | | | | Retrospective: the DASH prototype: implementation and performance
Daniel E. Lenoski, James P. Laudon
Pages: 80 - 82
Full text available: Pdf(345 KB) | | | | Retrospective: active messages: a mechanism for integrating computation and communication
Thorsten von Eicken, David E. Culler, Klaus Erik Schauser, Seth Copen Goldstein
Pages: 83 - 84
Full text available: Pdf(294 KB) | | | | Retrospective: the turn model for adaptive routing
Lionel Ni
Pages: 85 - 86
Full text available: Pdf(178 KB) | | | | Retrospective: alternative implementations of two-level adaptive training branch prediction
Tse-Yu Yeh, Yale N. Patt
Pages: 87 - 88
Full text available: Pdf(220 KB) | | | | Retrospective: the Cedar system
A. Veidenbaum, P.-C. Yew, D. J. Kuck, C. D. Polychronopoulos, D. H. Padua, E. S. Davidson, K. Gallivan
Pages: 89 - 91
Full text available: Pdf(384 KB) | | | | Retrospective: virtual memory mapped network interface for the SHRIMP multicomputer
Matthias A. Blumrich, Kai Li, Richard D. Alpert, Cezary Dubnicki, Edward W. Felten, Jonathan Sandberg
Pages: 92 - 94
Full text available: Pdf(382 KB) | | | | Retrospective: the Stanford FLASH multiprocessor
Jeffrey S. Kuskin
Pages: 95 - 97
Full text available: Pdf(309 KB) | | | | Retrospective: tempest and typhoon: user-level shared memory
Steven K. Reinhardt, James R. Larus, David A. Wood
Pages: 98 - 102
Full text available: Pdf(567 KB) | | | | Retrospective: the MIT Alewife machine: architecture and performance
Anant Agarwal
Pages: 103 - 110
Full text available: Pdf(1.02 MB) | | | | Retrospective: multiscalar processors
Gurindar Sohi
Pages: 111 - 114
Full text available: Pdf(463 KB) | | | | Retrospective: simultaneous multithreading: maximizing on-chip parallelism
Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
Pages: 115 - 116
Full text available: Pdf(176 KB) | | | | Banyan networks for partitioning multiprocessor systems
L. Rodney Goke, G. J. Lipovski
Pages: 117 - 124
Full text available: Pdf(996 KB) | | | | A preliminary architecture for a basic data-flow processor
Jack B. Dennis, David P. Misunas
Pages: 125 - 131
Full text available: Pdf(788 KB) | | | | Improving the throughput of a pipeline by insertion of delays
Janak H. Patel, Edward S. Davidson
Pages: 132 - 137
Full text available: Pdf(682 KB) | | | | Computer structures: what have we learned from the PDP-11?
Gordon Bell, William D. Strecker
Pages: 138 - 151
Full text available: Pdf(1.14 MB) | | | | An instruction timing model of CPU performance
Bernard L. Peuto, Leonard J. Shustek
Pages: 152 - 165
Full text available: Pdf(1.73 MB) | | | | Retrospective on high-level language computer architecture
David R. Ditzel, David A. Patterson
Pages: 166 - 173
Full text available: Pdf(886 KB) | | | | Architecture of a massively parallel processor
Kenneth E. Batcher
Pages: 174 - 179
Full text available: Pdf(672 KB) | | | | A processor for a high-performance personal computer
Butler W. Lampson, Kenneth A. Pier
Pages: 180 - 194
Full text available: Pdf(1.57 MB) | | | | Lockup-free instruction fetch/prefetch cache organization
David Kroft
Pages: 195 - 201
Full text available: Pdf(449 KB) | | | | A study of branch prediction strategies
James E. Smith
Pages: 202 - 215
Full text available: Pdf(917 KB) | | | | RISC I: a reduced instruction set VLSI computer
David A. Patterson, Carlo H. Sequin
Pages: 216 - 230
Full text available: Pdf(1.19 MB) | | | | Decoupled access/execute computer architectures
James E. Smith
Pages: 231 - 238
Full text available: Pdf(880 KB) | | | | The NYU ultracomputer—designing a MIMD, shared-memory parallel machine
Allan Gottlieb, Ralph Grishman, Clyde P. Kruskal, Kevin P. McAuliffe, Larry Rudolph, Marc Snir
Pages: 239 - 254
Full text available: Pdf(1.74 MB) | | | | Using cache memory to reduce processor-memory traffic
James R. Goodman
Pages: 255 - 262
Full text available: Pdf(1.08 MB) | | | | Very long instruction work architectures and the ELI-512
Joseph A. Fisher
Pages: 263 - 273
Full text available: Pdf(1.00 MB) | | | | A characterization of processor performance in the VAX-11/780
Joel S. Emer, Douglas W. Clark
Pages: 274 - 283
Full text available: Pdf(1.12 MB) | | | | A low-overhead coherence solution for multiprocessors with private cache memories
Mark S. Papamarcos, Janak H. Patel
Pages: 284 - 290
Full text available: Pdf(708 KB) | | | | Implementation of precise interrupts in pipelined processors
James E. Smith, Andrew R. Pleszkun
Pages: 291 - 299
Full text available: Pdf(1.07 MB) | | | | HPSm, a high performance restricted data flow architecture having minimal functionality
Wen-Wei Hwu, Yale N. Patt
Pages: 300 - 308
Full text available: Pdf(983 KB) | | | | Warp architecture and implementation
Marco Annaratone, Emmanuel Arnould, Thomas Gross, H. T. Kung, Monica S. Lam, Onat Menzilcioglu, Ken Sarocky, Jon A. Webb
Pages: 309 - 319
Full text available: Pdf(1.17 MB) | | | | Memory access buffering in multiprocessors
Michel Dubois, Christoph Scheurich, Faye Briggs
Pages: 320 - 328
Full text available: Pdf(1.10 MB) | | | | Instruction issue logic for high-performance, interruptable pipelined processors
Gurindar S. Sohi, Sriram Vajapeyam
Pages: 329 - 336
Full text available: Pdf(1.05 MB) | | | | Architecture of a message-driven processor
William J. Dally, Linda Chao, Andrew Chien, Soha Hassoun, Waldemar Horwat, Jon Kaplan, Paul Song, Brian Totty, Scott Wills
Pages: 337 - 344
Full text available: Pdf(848 KB) | | | | On the inclusion properties for multi-level cache hierarchies
Jean-Loup Baer, Wen-Hann Wang
Pages: 345 - 352
Full text available: Pdf(877 KB) | | | | An evaluation of directory schemes for cache coherence
Anant Agarwal, Richard Simoni, John Hennessy, Mark Horowitz
Pages: 353 - 362
Full text available: Pdf(1.31 MB) | | | | Weak ordering—a new definition
Sarita V. Adve, Mark D. Hill
Pages: 363 - 375
Full text available: Pdf(1.55 MB) | | | | Memory consistency and event ordering in scalable shared-memory multiprocessors
Kourosh Gharachorloo, Daniel Lenoski, James Laudon, Phillip Gibbons, Anoop Gupta, John Hennessy
Pages: 376 - 387
Full text available: Pdf(1.66 MB) | | | | Improving direct-mapped cache performance by the addition of a small fully-associative cache prefetch buffers
Norman P. Jouppi
Pages: 388 - 397
Full text available: Pdf(1.26 MB) | | | | Monsoon: an explicit token-store architecture
Gregory M. Papadopoulos, David E. Culler
Pages: 398 - 407
Full text available: Pdf(1.16 MB) | | | | IMPACT: an architectural framework for multiple-instruction-issue processors
Pohua P. Chang, Scott A. Mahlke, William Y. Chen, Nancy J. Warter, Wen-mei W. Hwu
Pages: 408 - 417
Full text available: Pdf(910 KB) | | | | The DASH prototype: implementation and performance
Daniel Lenoski, James Laudon, Truman Joe, David Nakahira, Luis Stevens, Anoop Gupta, John Hennessy
Pages: 418 - 429
Full text available: Pdf(1.52 MB) | | | | Active messages: a mechanism for integrating communication and computation
Thorsten von Eicken, David E. Culler, Seth Copen Goldstein, Klaus Erik Schauser
Pages: 430 - 440
Full text available: Pdf(1.47 MB) | | | | The turn model for adaptive routing
Christopher J. Glass, Lionel M. Ni
Pages: 441 - 450
Full text available: Pdf(1.08 MB) | | | | Alternative implementations of two-level adaptive branch prediction
Tse-Yu Yeh, Yale N. Patt
Pages: 451 - 461
Full text available: Pdf(1.39 MB) | | | | The Cedar system and an initial performance study
D. Kuck, E. Davidson, D. Lawrie, A. Sameh, C.-Q. Zhu, A. Veidenbaum, J. Konicek, P. Yew, K. Gallivan, W. Jalby, H. Wijshoff, R. Bramley, U. M. Yang, P. Emrath, D. Padua, R. Eigenmann, J. Hoeflinger, G. Jayson, Z. Li, T. Murphy, J. Andrews
Pages: 462 - 472
Full text available: Pdf(1.22 MB) | | | | Virtual memory mapped network interface for the SHRIMP multicomputer
Matthias A. Blumrich, Kai Li, Richard Alpert, Cezary Dubnicki, Edward W. Felten, Jonathan Sandberg
Pages: 473 - 484
Full text available: Pdf(1.39 MB) | | | | The Stanford FLASH multiprocessor
Jeffrey Kuskin, David Ofelt, Mark Heinrich, John Heinlein, Richard Simoni, K. Gharachorloo, J. Chapin, D. Nakahira, J. Baxter, M. Horowitz, A. Gupta, M. Rosenblum, J. Hennessy
Pages: 485 - 496
Full text available: Pdf(1.48 MB) | | | | Tempest and typhoon: user-level shared memory
Steven K. Reinhardt, James R. Larus, David A. Wood
Pages: 497 - 508
Full text available: Pdf(1.57 MB) | | | | The MIT Alewife machine: architecture and performance
Anant Agarwal, Ricardo Bianchini, David Chaiken, Kirk L. Johnson, David Kranz, J. Kubiatowicz, B.-H. Lim, K. Mackenzie, D. Yeung
Pages: 509 - 520
Full text available: Pdf(1.58 MB) | | | | Multiscalar processors
Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar
Pages: 521 - 532
Full text available: Pdf(1.57 MB) | | | | Simultaneous multithreading: maximizing on-chip parallelism
Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
Pages: 533 - 544
Full text available: Pdf(1.48 MB) | |
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