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International Symposium on Computer Architecture archive
Proceedings of the 25th annual international symposium on Computer architecture
1998,  Barcelona, Spain    June 27 - July 02, 1998
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Chairmen  
Mateo Valero Univ. Politecnica de Catalunya
Gurindar S. Sohi Univ. of Wisconsin-Madison, Madison
Editors  
 
Table of Contents
  General Chair's Message
Page: .09
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  Program Chair's Message
Page: .10
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  Conference Organization
Page: .11
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  Referees
Page: .12
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  Memory system characterization of commercial workloads
Luiz André Barroso, Kourosh Gharachorloo, Edouard Bugnion
Pages: 3 - 14
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  Performance characterization of a Quad Pentium Pro SMP using OLTP workloads
Kimberly Keeton, David A. Patterson, Yong Qiang He, Roger C. Raphael, Walter E. Baker
Pages: 15 - 26
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  Execution characteristics of desktop applications on Windows NT
Dennis C. Lee, Patrick J. Crowley, Jean-Loup Baer, Thomas E. Anderson, Brian N. Bershad
Pages: 27 - 38
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  An analysis of database workload performance on simultaneous multithreaded processors
Jack L. Lo, Luiz André Barroso, Susan J. Eggers, Kourosh Gharachorloo, Henry M. Levy, Sujay S. Parekh
Pages: 39 - 50
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  An analysis of correlation and predictability: what makes two-level branch predictors work
Marius Evers, Sanjay J. Patel, Robert S. Chappell, Yale N. Patt
Pages: 52 - 61
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  Branch prediction based on universal data compression algorithms
Eitan Federovsky, Meir Feder, Sholomo Weiss
Pages: 62 - 72
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  Modeling program predictability
Yiannakis Sazeides, James E. Smith
Pages: 73 - 84
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  Multi-level texture caching for 3D graphics hardware
Michael Cox, Narendra Bhandari, Michael Shantz
Pages: 86 - 97
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  Switcherland: a QoS communication architecture for workstation clusters
Hans Eberle, Erwin Oertli
Pages: 98 - 108
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  Declustered disk array architectures with optimal and near-optimal parallelism
Guillermo A. Alvarez, Walter A. Burkhard, Larry J. Stockmeyer, Flaviu Cristian
Pages: 109 - 120
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  Confidence estimation for speculation control
Dirk Grunwald, Artur Klauser, Srilatha Manne, Andrew Pleszkun
Pages: 122 - 131
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  Pipeline gating: speculation control for energy reduction
Srilatha Manne, Artur Klauser, Dirk Grunwald
Pages: 132 - 141
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  Memory dependence prediction using store sets
George Z. Chrysos, Joel S. Emer
Pages: 142 - 153
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  Dynamic history-length fitting: a third level of adaptivity for branch prediction
Toni Juan, Sanji Sanjeevan, Juan J. Navarro
Pages: 155 - 166
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  Accurate indirect branch prediction
Karel Driesen, Urs Hölzle
Pages: 167 - 178
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  Using prediction to accelerate coherence protocols
Shubhendu S. Mukherjee, Mark D. Hill
Pages: 179 - 190
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  Active pages: a computation model for intelligent memory
Mark Oskin, Frederic T. Chong, Timothy Sherwood
Pages: 192 - 203
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  Increasing TLB reach using superpages backed by shadow memory
Mark Swanson, Leigh Stoller, John Carter
Pages: 204 - 213
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  Options for dynamic address translation in COMAs
Xiaogang Qiu, Michel Dubois
Pages: 214 - 225
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  Integrated predicated and speculative execution in the IMPACT EPIC architecture
David I. August, Daniel A. Connors, Scott A. Mahlke, John W. Sias, Kevin M. Crozier, Ben-Chung Cheng, Patrick R. Eaton, Qudus B. Olaniran, Wen-mei W. Hwu
Pages: 227 - 237
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  Threaded multiple path execution
Steven Wallace, Brad Calder, Dean M. Tullsen
Pages: 238 - 249
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  Selective eager execution on the PolyPath architecture
Artur Klauser, Abhijit Paithankar, Dirk Grunwald
Pages: 250 - 259
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  Improving trace cache effectiveness with branch promotion and trace packing
Sanjay Jeram Patel, Marius Evers, Yale N. Patt
Pages: 262 - 271
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  The effect of instruction fetch bandwidth on value prediction
Freddy Gabbay, Avi Mendelson
Pages: 272 - 281
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  Dynamic IPC/clock rate optimization
David H. Albonesi
Pages: 282 - 292
 
  Performance modeling and code partitioning for the DS architecture
Yinong Zhang, George B. Adams, III
Pages: 293 - 304
 
  Exploiting fine-grain thread level parallelism on the MIT multi-ALU processor
Stephen W. Keckler, William J. Dally, Daniel Maskit, Nicholas P. Carter, Andrew Chang, Whay S. Lee
Pages: 306 - 317
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  Effects of architectural and technological advances on the HP/Convex Exemplar's memory and communication performance
Gheith A. Abandah, Edward S. Davidson
Pages: 318 - 329
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  Design choices in the SHRIMP system: an empirical study
Matthias A. Blumrich, Richard D. Alpert, Yuqun Chen, Douglas W. Clark, Stefanos N. Damianakis, Cezary Dubnicki, Edward W. Felten, Liviu Iftode, Kai Li, Margaret Martonosi, Robert A. Shillner
Pages: 330 - 341
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  Flexible use of memory for replication/migration in cache-coherent DSM multiprocessors
Vijayaraghavan Soundararajan, Mark Heinrich, Ben Verghese, Kourosh Gharachorloo, Anoop Gupta, John Hennessy
Pages: 342 - 355
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  Exploiting spatial locality in data caches using spatial footprints
Sanjeev Kumar, Christopher Wilkerson
Pages: 357 - 368
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  Low load latency through sum-addressed memory (SAM)
William L. Lynch, Gary Lauterbach, Joseph I. Chamdani
Pages: 369 - 379
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  Analytic evaluation of shared-memory systems with ILP processors
Daniel J. Sorin, Vijay S. Pai, Sarita V. Adve, Mary K. Vernon, David A. Wood
Pages: 380 - 391
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  Index of Authors
Page: 393
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