| | International Symposium on Low Power Electronics and Design archiveProceedings of the 1996 international symposium on Low power electronics and design 1996, Monterey, California, United States August 12 - 14, 1996 | | | Table of Contents | | | | The design of a high performance low power microprocessor
Dan Dobberpuhl
Pages: 11 - 16
Full text available:  Pdf(334 KB) | | | | Low power systems for wireless microsensors
K. Bult, A. Burstein, D. Chang, M. Dong, M. Fielding, E. Kruglick, J. Ho, F. Lin, T. Lin, W. Kaiser, H. Marcy, R. Mukai, P. Nelson, F. Newburg, K. Pister, G. Pottie, H. Sanchez, O. Stafsudd, K. Tan, S. Xue, J. Yao
Pages: 17 - 21
Full text available: Pdf(1.08 MB) | | | | A low power architecture for wireless multimedia systems: lessons learned from building a power hog
W. Mangione-Smith, P. Ghang, S. Nazareth, P. Lettieri, W. Boring, Rajeev Jain
Pages: 23 - 28
Full text available: Pdf(464 KB) | | | | High-level power estimation
Paul Landman
Pages: 29 - 35
Full text available: Pdf(70 KB) | | | | A power metric for mobile systems
T. Martin, D. Siewiorek
Pages: 37 - 42
Full text available: Pdf(50 KB) | | | | Lower bounds on power dissipation for DSP algorithms
N. Shanbhag
Pages: 43 - 48
Full text available: Pdf(265 KB) | | | | A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes
H. Yamauchi, T. Iwata, H. Akamatsu, A. Matsuzawa
Pages: 49 - 54
Full text available: Pdf(44 KB) | | | | Energy recovery for the design of high-speed, low-power static RAMs
N. Tzartzanis, W. Athas
Pages: 55 - 60
Full text available: Pdf(62 KB) | | | | A 1-V 1-Mb SRAM for portable equipment
H. Morimura, N. Shibata
Pages: 61 - 66
Full text available: Pdf(542 KB) | | | | A novel methodology for transistor-level power estimation
S. Huang, K. Cheng, K. Chen, T. Lee
Pages: 67 - 72
Full text available: Pdf(221 KB) | | | | Statistical estimation of average power dissipation in CMOS VLSI circuits using nonparametric techniques
L. Yuan, C. Teng, S. Kang
Pages: 73 - 78
Full text available: Pdf(336 KB) | | | | Switching activity analysis for sequential circuits using Boolean approximation method
T. Uchino, F. Minami, M. Murakata, T. Mitsuhashi
Pages: 79 - 84
Full text available: Pdf(258 KB) | | | | Transition reduction in carry-save adder trees
P. Larsson, C. Nicol
Pages: 85 - 88
Full text available: Pdf(60 KB) | | | | 250–600 Mhz 12b digital filters in 0.8–0.25&mgr;m bulk and SOI CMOS technologies
L. Thon, G. Shahidi, W. Rausch, G. Coleman, D. Tang, D. Schepis, R. Schulz, F. Assadaraghi
Pages: 89 - 92
Full text available: Pdf(2.09 MB) | | | | A comparison of CMOS implementations of an asynchronous circuits primitive: the C-element
M. Shams, J. Ebergen, M. Elmasry
Pages: 93 - 96
Full text available: Pdf(244 KB) | | | | Design techniques for high performance, energy efficient control logic
Uming Ko, Anthony Hill, Poras T. Balsara
Pages: 97 - 100
Full text available: Pdf(103 KB) | | | | Energy-recovery CMOS for highly pipelined DSP designs
W. Athas, W. Liu, L. Svensson
Pages: 101 - 104
Full text available: Pdf(72 KB) | | | | A sub-CV2 pad driver with 10 ns transition time
L. Svensson, W. Athas, R. Wen
Pages: 105 - 108
Full text available: Pdf(118 KB) | | | | Gate-level current waveform simulation of CMOS integrated circuits
Alessandro Bogliolo, Luca Benini, Giovanni De Micheli, Bruno Riccó
Pages: 109 - 112
Full text available: Pdf(289 KB) | | | | Effects of correlations on accuracy of power analysis—an experimental study
P. Schneider, S. Krishnamoorthy
Pages: 113 - 116
Full text available: Pdf(106 KB) | | | | Basic experimentation on accuracy of power estimation for CMOS VLSI circuits
T. Ishihara, H. Yasuura
Pages: 117 - 120
Full text available: Pdf(83 KB) | | | | Simulation based architectural power estimation for PLA-based controllers
S. Katkoori, R. Vemuri
Pages: 121 - 124
Full text available: Pdf(637 KB) | | | | Short circuit power consumption of glitches
D. Rabe, W. Nebel
Pages: 125 - 128
Full text available: Pdf(84 KB) | | | | A graded-channel MOS (GCMOS) VLSI technology for low power DSP applications
J. Ma, H. Liang, M. Kaneshiro, C. Kyono, R. Pryor, K. Papworth, S. Cheng
Pages: 129 - 132
Full text available: Pdf(219 KB) | | | | Fabrication and performance of mesa interconnect
L. Carley, D. Guillou, S. Santhanam
Pages: 133 - 137
Full text available: Pdf(80 KB) | | | | Floating body effects in partially-depleted SOI CMOS circuits
P. Lu, J. Ji, C. Chuang, L. Wagner, C. Hsieh, J. Kuang, L. Hsu, M. Pelella, S. Chu, C. Anderson
Pages: 139 - 144
Full text available: Pdf(525 KB) | | | | An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuits
A. Chatterjee, M. Nandakumar, I. Chen
Pages: 145 - 150
Full text available: Pdf(347 KB) | | | | Concurrency-oriented optimization for low-power asynchronous systems
L. Plana, S. Nowick
Pages: 151 - 156
Full text available: Pdf(361 KB) | | | | Energy minimization using multiple supply voltages
J. Chang, M. Pedram
Pages: 157 - 162
Full text available: Pdf(373 KB) | | | | Symbolic computation of logic implications for technology-dependent low-power synthesis
R. Bahar, M. Burns, G. Hachtel, E. Macii, H. Shin, F. Somenzi
Pages: 163 - 168
Full text available: Pdf(360 KB) | | | | Integrated resynthesis for low power
Olivier Coudert, Ramsey Haddad
Pages: 169 - 174
Full text available: Pdf(241 KB) | | | | Which has greater potential power impact: high-level design and algorithms or innovative low power technology? (panel)
James Burr, Laszlo Gal, Ramsey Haddad, Jan Rabaey, Bruce Wooley
Page: 175 | | | | How to design low-power digital cellular phones
K. Mashiko
Pages: 177 - 180
Full text available: Pdf(247 KB) | | | | What is the state of the art in commercial EDA tools for low power?
K. Keutzer, O. Coudert, R. Haddad
Pages: 181 - 187
Full text available: Pdf(197 KB) | | | | Accurate evaluation of CMOS short-circuit power dissipation for short-channel devices
L. Bisdounis, O. Koufopavlou, S. Nikolaidis
Pages: 189 - 192
Full text available: Pdf(567 KB) | | | | Circuit techniques for low-power CMOS GSI
A. Bhavnagarwala, V. De, B. Austin, J. Meindl
Pages: 193 - 196
Full text available: Pdf(314 KB) | | | | Device design for low power electronics with accurate deep submicrometer LDD-MOSFET models
K. Chen, Y. Cheng, C. Hu
Pages: 197 - 200
Full text available: Pdf(286 KB) | | | | Energy delay analysis of partial product reduction methods for parallel multiplier implementation
R. V. K. Pillai, D. Al-Khalili, A. J. Al-Khalili
Pages: 201 - 204
Full text available: Pdf(64 KB) | | | | Low-power radix-4 divider
A. Nannarelli, T. Lang
Pages: 205 - 208
Full text available: Pdf(203 KB) | | | | Power comparisons for barrel shifters
K. Acken, M. Irwin, R. Owens
Pages: 209 - 212
Full text available: Pdf(238 KB) | | | | Interlaced accumulation programming for low power DSP
H. Kojima, A. Shridhar
Pages: 213 - 216
Full text available: Pdf(200 KB) | | | | Low-power adaptive filter architectures via strength reduction
M. Goel, N. Shanbhag
Pages: 217 - 220
Full text available: Pdf(263 KB) | | | | Leap frog multiplier
S. Mahant-Shetti, C. Lemonds, P. Balsara
Pages: 221 - 223
Full text available: Pdf(82 KB) | | | | Manufacturability of low power CMOS technology solutions
A. J. Strojwas, M. Quarantelli, J. Borel, C. Guardiani, G. Nicollini, G. Crisenza, B. Franzini, J. Wiart
Pages: 225 - 232
Full text available: Pdf(94 KB) | | | | Effects of random MOSFET parameter fluctuations on total power consumption
X. Tang, V. De, J. Meindl
Pages: 233 - 236
Full text available: Pdf(307 KB) | | | | The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits
M. Eisele, J. Berthold, D. Schmitt-Landsiedel, R. Mahnkopf
Pages: 237 - 242
Full text available: Pdf(344 KB) | | | | 12-b 125 MSPS CMOS D/A designed for spectral performance
D. Mercer, L. Singer
Pages: 243 - 246
Full text available: Pdf(223 KB) | | | | Implementation of a micro power 15-bit “floating-point” A/D converter
L. Grisoni, A. Heubi, P. Balsiger, F. Pellandini
Pages: 247 - 252
Full text available: Pdf(250 KB) | | | | Micro power “relative precision” 13 bits cyclic RSD A/D converter
A. Heubi, P. Balsiger, F. Pellandini
Pages: 253 - 257
Full text available: Pdf(94 KB) | | | | Fixed-phase retiming for low power design
M. Papaefthymiou, K. Lalgudi
Pages: 259 - 264
Full text available: Pdf(350 KB) | | | | Clock skew optimization for peak current reduction
P. Vuillod, L. Benini, A. Bogliolo, G. De Micheli
Pages: 265 - 270
Full text available: Pdf(345 KB) | | | | Simultaneous buffer and wire sizing for performance and power optimization
J. Cong, C. Koh, K. Leung
Pages: 271 - 276
Full text available: Pdf(223 KB) | | | | A low power high performance switched-current multiplier
D. M. W. Leenaerts, G. H. M. Joordens, J. A. Hegt
Pages: 277 - 280
Full text available: Pdf(77 KB) | | | | Low-power frequency multiplier with one cycle lock-in time and 100ppm frequency resolution, for system power-management
R. Fried, Z. Azmanov
Pages: 281 - 284
Full text available: Pdf(76 KB) | | | | A 1.5V class AB output buffer
Fan You, S. H. K. Embabi, Edgar Sánchez-Sinencio
Pages: 285 - 288
Full text available: Pdf(278 KB) | | | | Low-power mapping of behavioral arrays to multiple memories
P. Panda, N. Dutt
Pages: 289 - 292
Full text available: Pdf(243 KB) | | | | Logic synthesis using power-sensitive don't care sets
C. Lennard, P. Buch, A. Newton
Pages: 293 - 296
Full text available: Pdf(147 KB) | | | | Gate-level synthesis for low-power using new transformations
D. Pradhan, M. Chatterjee, M. Swarna, W. Kunz
Pages: 297 - 300
Full text available: Pdf(433 KB) | | | | Controller re-specification to minimize switching activity in controller/data path circuits
A. Raghunathan, S. Dey, N. Jha, K. Wakabayashi
Pages: 301 - 304 | | | | A 200 &mgr;A, 78 MHz CMOS crystal-oscillator digitally trimmable to 0.3 ppm
Q. Huang, P. Basedau
Pages: 305 - 308
Full text available: Pdf(111 KB) | | | | Substrate noise influence on circuit performance in variable threshold-voltage scheme
Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Toshiaki Mori, Kenji Matsuo, Masakazu Kakumu, Takayasu Sakurai
Pages: 309 - 312
Full text available: Pdf(262 KB) | | | | A low power switching power supply for self-clocked systems
G. Wei, M. Horowitz
Pages: 313 - 317
Full text available: Pdf(613 KB) | | | | Design of a programmable temperature monitoring device for tagging small fish
Godi Fischer, James C. Daly, Chun Yang, Conrad W. Recksiek, Kevin D. Friedland
Pages: 319 - 322
Full text available: Pdf(294 KB) | | | | Entropic bounds on FSM switching
A. Tyagi
Pages: 323 - 328
Full text available: Pdf(377 KB) | | | | High-level power estimation and the area complexity of Boolean functions
M. Nemani, F. Najm
Pages: 329 - 334
Full text available: Pdf(271 KB) | | | | Two dimensional codes for low power
M. Stan, W. Burleson
Pages: 335 - 340
Full text available: Pdf(176 KB) | | | | Low power, testable dual edge triggered flip-flops
R. Llopis, M. Sachdev
Pages: 341 - 345
Full text available: Pdf(58 KB) | | | | Data driven signal processing: an approach for energy efficient computing
A. Chandrakasan, V. Gutnik, T. Xanthopoulos
Pages: 347 - 352
Full text available: Pdf(524 KB) | | | | Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer
M. Hiraki, R. Bajwa, H. Kojima, D. Gorny, K. Nitta, A. Shridhar, K. Sasaki, K. Seki
Pages: 353 - 358
Full text available: Pdf(537 KB) | | | | Power exploration for data dominated video applications
Sven Wuytack, Francky Catthoor, Lode Nachtergaele, Hugo De Man
Pages: 359 - 364
Full text available: Pdf(128 KB) | | | | Practical performance/power alternatives within an existing CMOS technology generation
Kerry Bernstein, John E. Bertsch, William F. Clark, John J. Ellis-Monaghan, Larry G. Heller, Edward J. Nowak
Pages: 365 - 370
Full text available: Pdf(69 KB) | | | | A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI)
V. De, J. Meindl
Pages: 371 - 375
Full text available: Pdf(362 KB) | | | | Comparison of high speed voltage-scaled conventional and adiabatic circuits
D. Frank
Pages: 377 - 380
Full text available: Pdf(134 KB) | | | | Static power driven voltage scaling and delay driven buffer sizing in mixed swing QuadRail for sub-1V I/O swings
R. Krishnamurthy, I. Lys, L. Carley
Pages: 381 - 386
Full text available: Pdf(227 KB) | |
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