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International Conference on Computer Aided Design archive
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
2007,  San Jose, California    November 05 - 08, 2007
Additional Information:full citation, abstract
Paper Acceptance Rate:139.00 of 510.00 submissions, 27%  view statistics
General Chair   
Georges Gielen ESAT-MICAS, Katholieke Univ. Leuven, Leuven, Belgium
Front matter
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Front matter (Title page, Copyright page, Foreword, Committees, Reviewers, Awards, Keynotes, Tutorials, Designers' perspective, TOC)

Back matter
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Back matter (Author index)
 
Table of Contents
 
SESSION: Advances in parasitic extraction and variability modeling
    A fast and high-capacity electromagnetic solution for highspeed IC design
Houle Gan, Dan Jiao
Pages 1-6
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    Impedance extraction for 3-D structures with multiple dielectrics using preconditioned boundary element method
Yang Yi, Peng Li, Vivek Sarin, Weiping Shi
Pages 7-10
Full text available: PdfPdf(109 KB)
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    Statistical analysis of RF circuits using combined circuit simulator-full wave field solver approach
Arun V Sathanur, Ritochit Chakraborty, Vikram Jandhyala
Pages 11-17
Full text available: PdfPdf(175 KB)
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SESSION: Networks-on-Chip and latency-insensitive systems
    Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip
Zhonghai Lu, Axel Jantsch
Pages 18-25
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    Run-time adaptive on-chip communication scheme
Mohammad Abdullah Al Faruque, Thomas Ebi, Jörg Henkel
Pages 26-31
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    Using functional independence conditions to optimize the performance of latency-insensitive systems
Cheng-Hong Li, Luca P. Carloni
Pages 32-39
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SESSION: Power grid analysis
    A geometric approach for early power grid verification using current constraints
Imad A. Ferzli, Farid N. Najm, Lars Kruse
Pages 40-47
Full text available: PdfPdf(283 KB)
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    Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks
Ning Mi, Sheldon X.-D. Tan, Pu Liu, Jian Cui, Yici Cai, Xianlong Hong
Pages 48-53
Full text available: PdfPdf(436 KB)
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    Parallel domain decomposition for simulation of large-scale power grids
Kai Sun, Quming Zhou, Kartik Mohanram, Danny C. Sorensen
Pages 54-59
Full text available: PdfPdf(137 KB)
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SESSION: Synthesis and verification of quantum circuits
    Fast exact Toffoli network synthesis of reversible logic
Robert Wille, Daniel Große
Pages 60-64
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    A novel synthesis algorithm for reversible circuits
Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani
Pages 65-68
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    Checking equivalence of quantum circuits and states
George F. Viamontes, Igor L. Markov, John P. Hayes
Pages 69-74
Full text available: PdfPdf(192 KB)
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SESSION: Connecting physical challenges and design approaches
    A self-adjusting clock tree architecture to cope with temperature variations
Jieyi Long, Ja Chun Ku, Seda Ogrenci Memik, Yehea Ismail
Pages 75-82
Full text available: PdfPdf(433 KB)
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    Exploiting STI stress for performance
Andrew B. Kahng, Puneet Sharma, Rasit O. Topaloglu
Pages 83-90
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    Automating post-silicon debugging and repair
Kai-hui Chang, Igor L. Markov, Valeria Bertacco
Pages 91-98
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    Practical method for obtaining a feasible integer solution in hierarchical layout optimization
Xiaoping Tang, Xin Yuan, Michael S. Gray
Pages 99-104
Full text available: PdfPdf(144 KB)
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SESSION: Analytical techniques for physical optimization
    Monte-Carlo driven stochastic optimization framework for handling fabrication variability
Vishal Khandelwal, Ankur Srivastava
Pages 105-110
Full text available: PdfPdf(186 KB)
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    Gate sizing by Lagrangian relaxation revisited
Jia Wang, Debasish Das, Hai Zhou
Pages 111-118
Full text available: PdfPdf(317 KB)
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    An efficient algorithm for statistical circuit optimization using Lagrangian relaxation
I-Jye Lin, Yao-Wen Chang
Pages 119-124
Full text available: PdfPdf(213 KB)
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    Unified adaptivity optimization of clock and logic signals
Shiyan Hu, Jiang Hu
Pages 125-130
Full text available: PdfPdf(152 KB)
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SESSION: Logic synthesis
    Incremental component implementation selection: enabling ECO in compositional system synthesis
Soheil Ghiasi
Pages 131-134
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    Exploiting hierarchy and structure to efficiently solve graph coloring as SAT
Miroslav N. Velev
Pages 135-142
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    Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors
Sivaram Gopalakrishnan, Priyank Kalla, M. Brandon Meredith, Florian Enescu
Pages 143-148
Full text available: PdfPdf(191 KB)
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    Enhancing design robustness with reliability-aware resynthesis and logic simulation
Smita Krishnaswamy, Stephen M. Plaza, Igor L. Markov, John P. Hayes
Pages 149-154
Full text available: PdfPdf(384 KB)
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SESSION: Memory optimization and system-level timing
    Data locality enhancement for CMPs
Mahmut Kandemir
Pages 155-159
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    Mapping model with inter-array memory sharing for multidimensional signal processing
Ilie I. Luican, Hongwei Zhu, Florin Balasa
Pages 160-165
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    Increasing data-bandwidth to instruction-set extensions through register clustering
Kingshuk Karuri, Anupam Chattopadhyay, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Pages 166-171
Full text available: PdfPdf(221 KB)
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    Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design
Philip Brisk, Ajay K. Verma, Paolo Ienne
Pages 172-179
Full text available: PdfPdf(223 KB)
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    An efficient algorithm for time separation of events in concurrent systems
Peggy B. McGee, Steven M. Nowick
Pages 180-187
Full text available: PdfPdf(238 KB)
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SESSION: Resilient and regular circuits
    Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
Yu Hu, Satyaki Das, Steve Trimberger, Lei He
Pages 188-193
Full text available: PdfPdf(249 KB)
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    Device and architecture concurrent optimization for FPGA transient soft error rate
Yan Lin, Lei He
Pages 194-198
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    Design methodology to trade off power, output quality and error resiliency: application to color interpolation filtering
Georgios Karakonstantis, Nilanjan Banerjee, Kaushik Roy, Chaitali Chakrabarti
Pages 199-204
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SESSION: 3-D integration challenges
    Thermal-aware Steiner routing for 3D stacked ICs
Mohit Pathak, Sung Kyu Lim
Pages 205-211
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    Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs
Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
Pages 212-219
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    Strategies for improving the parametric yield and profits of 3D ICs
Cesare Ferri, Sherief Reda, R. Iris Bahar
Pages 220-226
Full text available: PdfPdf(176 KB)
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SESSION: Applications of SAT and QBF
    Scalable exploration of functional dependency by interpolation and incremental SAT solving
Chih-Chun Lee, Jie-Hong R. Jiang, Chung-Yang (Ric) Huang, Alan Mishchenko
Pages 227-233
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    Incremental learning approach and SAT model for Boolean matching with don't cares
Kuo-Hua Wang, Chung-Ming Chan
Pages 234-239
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    A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test
Hratch Mangassarian, Andreas Veneris, Sean Safarpour, Marco Benedetti, Duncan Smith
Pages 240-245
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SESSION: Physical synthesis comes of age
    The coming of age of physical synthesis
Charles J. Alpert, Chris Chu, Paul G. Villarrubia
Pages 246-249
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SESSION: High quality test cases for verification
    An incremental learning framework for estimating signal controllability in unit-level verification
Charles H.-P. Wen, Li-C. Wang, Jayanta Bhadra
Pages 250-257
Full text available: PdfPdf(273 KB)
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    Stimulus generation for constrained random simulation
Nathan Kitchen, Andreas Kuehlmann
Pages 258-265
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    Probabilistic decision diagrams for exact probabilistic analysis
Afshin Abdollahi
Pages 266-272
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    Computation of minimal counterexamples by using black box techniques and symbolic methods
Tobias Nopper, Christoph Scholl, Bernd Becker
Pages 273-280
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SESSION: Advances in embedded systems
    Approximation algorithm for the temperature-aware scheduling problem
Sushu Zhang, Karam S. Chatha
Pages 281-288
Full text available: PdfPdf(425 KB)
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    Procrastination determination for periodic real-time tasks in leakage-aware dynamic voltage scaling systems
Jian-Jia Chen, Tei-Wei Kuo
Pages 289-294
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    The FAST methodology for high-speed SoC/computer simulation
Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil Patil, William H. Reinhart, D. Eric Johnson, Zheng Xu
Pages 295-302
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    A novel SoC design methodology combining adaptive software and reconfigurable hardware
Marco D. Santambrogio, Seda Ogrenci Memik, Vincenzo Rana, Umut A. Acar, Donatella Sciuto
Pages 303-308
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SESSION: Can nano-photonic silicon circuits become an intra-chip interconnect technology?
    Can nano-photonic silicon circuits become an INTRA-chip interconnect technology?
Eli Yablonovitch
Pages 309-309
Full text available: PdfPdf(105 KB)
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SESSION: Scaling formal verification
    Hybrid CEGAR: combining variable hiding and predicate abstraction
Chao Wang, Hyondeuk Kim, Aarti Gupta
Pages 310-317
Full text available: PdfPdf(231 KB)
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    Automated refinement checking of concurrent systems
Sudipta Kundu, Sorin Lerner, Rajesh Gupta
Pages 318-325
Full text available: PdfPdf(223 KB)
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    Inductive equivalence checking under retiming and resynthesis
Jie-Hong R. Jiang, Wei-Lun Hung
Pages 326-333
Full text available: PdfPdf(258 KB)
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SESSION: Advances in statistical timing analysis and optimization
    A frequency-domain technique for statistical timing analysis of clock meshes
Ruilin Wang, Cheng-Kok Koh
Pages 334-339
Full text available: PdfPdf(306 KB)
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    Clustering based pruning for statistical criticality computation under process variations
Hushrav D Mogal, Haifeng Qian, Sachin S Sapatnekar, Kia Bazargan
Pages 340-343
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    Timing budgeting under arbitrary process variations
Ruiming Chen, Hai Zhou
Pages 344-349
Full text available: PdfPdf(216 KB)
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SESSION: Sequential synthesis and FPGA mapping
    Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping
Yu Hu, Victor Shih, Rupak Majumdar, Lei He
Pages 350-353
Full text available: PdfPdf(206 KB)
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    Combinational and sequential mapping with priority cuts
Alan Mishchenko, Sungmin Cho, Satrajit Chatterjee, Robert Brayton
Pages 354-361
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    A general model for performance optimization of sequential systems
Dmitry Bufistov, Jordi Cortadella, Mike Kishinevsky, Sachin Sapatnekar
Pages 362-369
Full text available: PdfPdf(268 KB)
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    Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains
Lei Cheng, Deming Chen, Martin D. F. Wong, Mike Hutton, Jason Govig
Pages 370-375
Full text available: PdfPdf(318 KB)
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SESSION: Advances in routing and clock design
    Skew aware polarity assignment in clock tree
Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang
Pages 376-379
Full text available: PdfPdf(222 KB)
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    Efficient multi-layer obstacle-avoiding rectilinear Steiner tree construction
Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu, Meng-Xiang Li, Yao-Wen Chang
Pages 380-385
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    A simultaneous bus orientation and bused pin flipping algorithm
Fan Mo, Robert K. Brayton
Pages 386-389
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    Optimal bus sequencing for escape routing in dense PCBs
Hui Kong, Tan Yan, Martin D. F. Wong, Muhammet Mustafa Ozdal
Pages 390-395
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    Untangling twisted nets for bus routing
Tan Yan, Martin D. F. Wong
Pages 396-400
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SESSION: Improving delay test generation and performance predictors
    Low-overhead design technique for calibration of maximum frequency at multiple operating points
Somnath Paul, Sivasubramaniam Krishnamurthy, Hamid Mahmoodi, Swarup Bhunia
Pages 401-404
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    Variation-aware performance verification using at-speed structural test and statistical timing
Vikram Iyengar, Jinjun Xiong, Subbayyan Venkatesan, Vladimir Zolotov, David Lackey, Peter Habitz, Chandu Visweswariah
Pages 405-412
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    Estimation of delay test quality and its application to test generation
Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo
Pages 413-417
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    Efficient path delay test generation based on stuck-at test generation using checker circuitry
Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara
Pages 418-423
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SESSION: High level synthesis
    Timing variation-aware high-level synthesis
Jongyoon Jung, Taewhan Kim
Pages 424-428
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    Early planning for clock skew scheduling during register binding
Min Ni, Seda Ogrenci Memik
Pages 429-434
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    Compatibility path based binding algorithm for interconnect reduction in high level synthesis
Taemin Kim, Xun Liu
Pages 435-441
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    Operation chaining asynchronous pipelined circuits
Girish Venkataramani, Seth C. Goldstein
Pages 442-449
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SESSION: Analog circuit optimization
    Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization
Xin Li, Brian Taylor, YuTsun Chien, Lawrence T. Pileggi
Pages 450-457
Full text available: PdfPdf(316 KB)
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    Sensitivity analysis for oscillators
Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
Pages 458-463
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    Yield-aware analog integrated circuit optimization using geostatistics motivated performance modeling
Guo Yu, Peng Li
Pages 464-469
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    Device-circuit co-optimization for mixed-mode circuit design via geometric programming
Jintae Kim, Ritesh Jhaveri, Jason Woo, Chih-Kong Ken Yang
Pages 470-475
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    Modeling, optimization and control of rotary traveling-wave oscillator
Cheng Zhuo, Huafeng Zhang, Rupak Samanta, Jiang Hu, Kangsheng Chen
Pages 476-480
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SESSION: Global routing
    A methodology for fast and accurate yield factor estimation during global routing
Subarna Sinha, Charles C. Chiang
Pages 481-487
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    Archer: a history-driven global routing algorithm
Muhammet Mustafa Ozdal, Martin D. F. Wong
Pages 488-495
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    High-performance routing at the nanometer scale
Jarrod A. Roy, Igor L. Markov
Pages 496-502
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    BoxRouter 2.0: architecture and implementation of a hybrid and robust global router
Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan
Pages 503-508
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SESSION: Test compression and test power
    CacheCompress: a novel approach for test data compression with cache for IP embedded cores
Hao Fang, Chenguang Tong, Bo Yao, Xiaodi Song, Xu Cheng
Pages 509-512
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    A hybrid scheme for compacting test responses with unknown values
Mango C.-T. Chao, Kwang-Ting Cheng, Seongmoon Wang, Srimat T. Chakradhar, Wen-Long Wei
Pages 513-519
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    A selective pattern-compression scheme for power and test-data reduction
Chia-Yi Lin, Hung-Ming Chen
Pages 520-525
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    Methodology for low power test pattern generation using activity threshold control logic
Srivaths Ravi, V. R. Devanathan, Rubin Parekhji
Pages 526-529
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SESSION: Gate level physical synthesis
    ECO timing optimization using spare cells
Yen-Pin Chen, Jia-Wei Fang, Yao-Wen Chang
Pages 530-535
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    Timing optimization by restructuring long combinatorial paths
Jürgen Werber, Dieter Rautenbach, Christian Szegedy
Pages 536-543
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    Engineering change using spare cells with constant insertion
Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska
Pages 544-547
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    Simultaneous input vector selection and dual threshold voltage assignment for static leakage minimization
Lin Yuan, Gang Qu
Pages 548-551
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SESSION: Interconnect modeling and optimization
    Equalized interconnects for on-chip networks: modeling and optimization framework
Byungsub Kim, Vladimir Stojanović
Pages 552-559
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    IntSim: A CAD tool for optimization of multilevel interconnect networks
Deepak C. Sekar, Azad Naeemi, Reza Sarvari, Jeffrey A. Davis, James D. Meindl
Pages 560-567
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    A fast band-matching technique for interconnect inductance modeling
Hong Li, Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan
Pages 568-571
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SESSION: Formal verification at higher levels of abstraction
    Formal verification at higher levels of abstraction
Daniel Kroening, Sanjit A. Seshia
Pages 572-578
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SESSION: Floorplanning
    Analog placement with common centroid constraints
Qiang Ma, Evangeline F. Y. Young, K. P. Pun
Pages 579-585
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    Temperature aware microprocessor floorplanning considering application dependent power load
Chun-Ta Chu, Xinyi Zhang, Lei He, Tom Tong Jing
Pages 586-589
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    3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits
Pingqiang Zhou, Yuchun Ma, Zhouyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou
Pages 590-597
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SESSION: System-level synthesis and interconnect design
    Variation-aware task allocation and scheduling for MPSoC
Feng Wang, C. Nicopoulos, Xiaoxia Wu, Yuan Xie, N. Vijaykrishnan
Pages 598-603
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    A design flow dedicated to multi-mode architectures for DSP applications
Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin
Pages 604-611
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    The design and synthesis of a synchronous and distributed MAC protocol for wireless network-on-chip
Yi Wang, Dan Zhao
Pages 612-617
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    Selective shielding: a crosstalk-free bus encoding technique
Madhu Mutyam
Pages 618-621
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SESSION: Advances in model order reduction techniques for interconnect analysis
    Sparse and passive reduction of massively coupled large multiport interconnects
Natalie Nakhla, Michel Nakhla, Ram Achar
Pages 622-626
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    Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding
Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu
Pages 627-631
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    Principle Hessian direction based parameter reduction with process variation
Alex Mitev, Michael Marefat, Dongsheng Ma, Janet M. Wang
Pages 632-637
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SESSION: Mosfet modeling for 45nm & beyond
    MOSFET modeling for 45nm and beyond
Yu Cao, Colin McAndrew
Pages 638-643
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SESSION: Voltage assignment in floorplanning
    Voltage island-driven floorplanning
Qiang Ma, Evangeline F. Y. Young
Pages 644-649
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    An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning
Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang
Pages 650-655
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    Module assignment for pin-limited designs under the stacked-Vdd paradigm
Yong Zhan, Tianpei Zhang, Sachin S. Sapatnekar
Pages 656-659
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SESSION: Variation tolerant circuits
    Yield-driven near-threshold SRAM design
Gregory K. Chen, David Blaauw, Trevor Mudge, Dennis Sylvester, Nam Sung Kim
Pages 660-666
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    Soft-edge flip-flops for improved timing yield: design and optimization
Vivek Joshi, David Blaauw, Dennis Sylvester
Pages 667-673
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    Remote activation of ICs for piracy prevention and digital right management
Yousra Alkabani, Farinaz Koushanfar, Miodrag Potkonjak
Pages 674-677
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SESSION: Advanced models for static timing analysis
    A nonlinear cell macromodel for digital applications
Chandramouli Kashyap, Chirayu Amin, Noel Menezes, Eli Chiprout
Pages 678-685
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    Including inductance in static timing analysis
Ahmed Shebaita, Dusan Petranovic, Yehea Ismail
Pages 686-691
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    A robust finite-point based gate model considering process variations
Alex Mitev, Dinesh Ganesan, Dheepan Shanmugasundaram, Yu Cao, Janet M. Wang
Pages 692-697
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    Victim alignment in crosstalk aware timing analysis
Ravikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat Becer, Joao Geada
Pages 698-704
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SESSION: Variation aware timing verification
    Compact modeling of variational waveforms
V. Zolotov, J. Xiong, S. Abbaspour, D. J. Hathaway, C. Visweswariah
Pages 705-712
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    Multi-layer interconnect performance corners for variation-aware timing analysis
Frank Huebbers, Ali Dasdan, Yehea Ismail
Pages 713-718
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    An efficient method for statistical circuit simulation
Frank Liu
Pages 719-724
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    A methodology for timing model characterization for statistical static timing analysis
Zhuo Feng, Peng Li
Pages 725-729
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SESSION: Reliability driven modeling and analysis for deep submicron technologies
    Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance
Kunhyuk Kang, Sang Phill Park, Kaushik Roy, Muhammad A. Alam
Pages 730-734
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    An efficient method to identify critical gates under circuit aging
Wenping Wang, Zile Wei, Shengqi Yang, Yu Cao
Pages 735-740
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    Efficient computation of current flow in signal wires for reliability analysis
Kanak Agarwal, Frank Liu
Pages 741-746
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    The effect of process variation on device temperature in FinFET circuits
Jung Hwan Choi, Jayathi Murthy, Kaushik Roy
Pages 747-751
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SESSION: Design automation and defect tolerance techniques for emerging technologies
    BioRoute: a network-flow based routing algorithm for digital microfluidic biochips
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
Pages 752-757
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    Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture
Chen Dong, Deming Chen, Sansiri Tanachutiwat, Wei Wang
Pages 758-764
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    Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays
M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli
Pages 765-772
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    Combining static and dynamic defect-tolerance techniques for nanoscale memory systems
Susmit Biswas, Gang Wang, Tzvetan S. Metodi, Ryan Kastner, Frederic T. Chong
Pages 773-778
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SESSION: Leakage power reduction
    An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon
Yu-Ting Chen, Da-Cheng Juan, Ming-Chao Lee, Shih-Chieh Chang
Pages 779-782
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    Analysis and optimization of power-gated ICs with multiple power gating configurations
Aida Todri, Malgorzata Marek-Sadowska, Shih-Chieh Chang
Pages 783-790
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    Sizing and placement of charge recycling transistors in MTCMOS circuits
Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram
Pages 791-796
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    Minimizing leakage power in sequential circuits by using mixed Vt flip-flops
Jaehyun Kim, Youngsoo Shin
Pages 797-802
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SESSION: Power modeling and optimization
    Efficient decoupling capacitance budgeting considering operation and process variations
Yiyu Shi, Jinjun Xiong, Chunchen Liu, Lei He
Pages 803-810
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    Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs
Mikhail Popovich, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin
Pages 811-816
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    A novel technique for incremental analysis of on-chip power distribution networks
Yuhong Fu, Rajendran Panda, Ben Reschke, Savithri Sundareswaran, Min Zhao
Pages 817-823
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    Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques
Xiaoyao Liang, Kerem Turgay, David Brooks
Pages 824-830
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SESSION: Improving planarity and patterning
    Novel wire density driven full-chip routing for CMP variation control
Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang, Yao-Wen Chang
Pages 831-838
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    Accurate detection for process-hotspots with vias and incomplete specification
Jingyu Xu, Subarna Sinha, Charles C. Chiang
Pages 839-846
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    TIP-OPC: a new topological invariant paradigm for pixel based optical proximity correction
Peng Yu, David Z. Pan
Pages 847-853
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    A novel intensity based optical proximity correction algorithm with speedup in lithography simulation
Peng Yu, David Z. Pan
Pages 854-859
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SESSION: Model order reduction for parameterized and non-linear systems
    Stabilizing schemes for piecewise-linear reduced order models via projection and weighting functions
Bradley N Bond, Luca Daniel
Pages 860-866
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    Parameterized model order reduction via a two-directional Arnoldi process
Yung-Ta Li, Zhaojun Bai, Yangfeng Su, Xuan Zeng
Pages 868-873
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    Efficient VCO phase macromodel generation considering statistical parametric variations
Wei Dong, Zhuo Feng, Peng Li
Pages 874-878
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    Bounding L2 gain system error generated by approximations of the nonlinear vector field
Kin Cheong Sou, Alexandre Megretski, Luca Daniel
Pages 879-886
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    Variable domain transformation for linear PAC analysis of mixed-signal systems
Jaeha Kim, Kevin D. Jones, Mark A. Horowitz
Pages 887-894
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