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1
Architectures and VLSI Implementations of the AES-Proposal Rijndael
December 2002
IEEE Transactions on Computers , Volume 51 Issue 12
Publisher: IEEE Computer Society
Full text available: Publisher SitePublisher Site
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Abstract¿Two architectures and VLSI implementations of the AES Proposal, Rijndael, are presented in this paper. These alternative architectures are operated both for encryption and decryption process. They reduce the required hardware resources and achieve ...


Keywords: AES, Rijndael, secret key ciphers, security, pipelining architectures.
2
Calculational derivation of a counter with bounded response time and bounded power dissipation
March 1995
Distributed Computing , Volume 8 Issue 3
Publisher: Springer-Verlag
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A counter is calculationally designed by applying a functional way of programming, in which a machine is conceived as a function from states to behaviours. The design exploits the fine-grained concurrency available in VLSI. It is obtained by applying ...


Keywords: asynchronous circuits, bounded response time, counters, distributed systems, handshake circuits, recursive designs, systolic designs, transformational design
3
A DAG clustering algorithm for design configurations
December 1987
ACM '87: Proceedings of the 1987 Fall Joint Computer Conference on Exploring technology: today and tomorrow
Publisher: IEEE Computer Society Press
Full text available: PdfPdf (1.13 MB)
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Bibliometrics:  Downloads (6 Weeks): 3,   Downloads (12 Months): 12,   Downloads (Overall): 112,    Citation Count: 0

Design configurations of objects in engineering design applications, such as VLSI CAD, mechanical CAD and software design systems, are complex compositions of alternatives and historical versions of other objects. Design configurations can be ...

4
Layout of a multiplexed electrode VLSI circuit for monitoring evoked responses in cerebral cortex
June 1987
Journal of Medical Systems , Volume 11 Issue 2-3
Publisher: Plenum Press
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5
Polymorphic multiple-processor networks
January 1992
Polymorphic multiple-processor networks
Publisher: University of Massachusetts
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Keywords: VLSI
6
CSG hidden surface algorithms for VLSI hardware systems
October 1987
Eurographic seminars; tutorials and perspectives in computer graphics on Advances in computer graphics hardware I
Publisher: Springer-Verlag
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7
Acknowledgements
April 2004
VTS '04: Proceedings of the 22nd IEEE VLSI Test Symposium
Publisher: IEEE Computer Society
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8
The mad-postman network chip
May 1991
Proceedings of the world transputer user group (WOTUG) conference on Transputing '91
Publisher: IOS Press
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9
Parallel algorithms for VLSI computer-aided design
January 1994
Parallel algorithms for VLSI computer-aided design
Publisher: Prentice-Hall, Inc.
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10
Fail-Safe Interfaces for VLSI: Theoretical Foundations and Implementation
January 1998
IEEE Transactions on Computers , Volume 47 Issue 1
Publisher: IEEE Computer Society
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11
An analog VLSI architecture for stereo correspondence
January 1994
An analog VLSI architecture for stereo correspondence
Publisher: California Institute of Technology
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Keywords: VLSI
12
Automated X-Ray Inspection of Aluminum Castings
January 1988
IEEE Transactions on Pattern Analysis and Machine Intelligence , Volume 10 Issue 1
Publisher: IEEE Computer Society
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The experience gained with several approaches to automatic flaw detection in X-ray images of cast aluminum wheels is described. Basic problems are mentioned, and the applicability of segmentation methods to actual inspection tasks is demonstrated. The ...


Keywords: Al alloys, X-ray images, automated inspection, automatic flaw detection, cast aluminum wheels, computerised pattern recognition, feature definition, feature extraction, flaw detection, inspection, mechanical engineering computing, pixel classification, segmentation methods
13
A System for PCB Automated Inspection Using Fluorescent Light
January 1988
IEEE Transactions on Pattern Analysis and Machine Intelligence , Volume 10 Issue 1
Publisher: IEEE Computer Society
Full text available: Publisher SitePublisher Site
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Research was performed on the detection of faults such as shorts, cuts, and nicks in a printed circuit board pattern. The possibility was investigated of detecting a pattern by illuminating a printed circuit board with violet or ultraviolet rays and ...


Keywords: PCB automated inspection, circuit analysis computing, computer vision, computerised pattern recognition, cuts, fault detection, fault location, fluorescence, fluorescent light, glass-epoxy, glass-polyimide, high-sensitivity TV camera, inspection, nicks, optical fiber, pattern recognition, printed circuit board pattern, printed circuit testing, short-circuits, silhouette image, ultraviolet rays, violet illumination
14
Efficient exploration of on-chip bus architectures and memory allocation
September 2004
CODES+ISSS '04: Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Publisher: ACM
Full text available: PdfPdf (594.85 KB)
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Bibliometrics:  Downloads (6 Weeks): 8,   Downloads (12 Months): 47,   Downloads (Overall): 420,    Citation Count: 5

Separation between computation and communication in system design allows the system designer to explore the communication architecture independently of component selection and mapping. In this paper we present an iterative two-step exploration methodology ...


Keywords: communication architecture optimization, design space exploration, memory allocation, system-on-a-chip
15
A VLSI prolog processor, design and methodology: a case study in high level language processor design
June 1994
A VLSI prolog processor, design and methodology: a case study in high level language processor design
Publisher: North-Holland Publishing Co.
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16
Journal of VLSI Signal Processing Systems: Volume 47 Issue 2
May 2007
Journal of VLSI Signal Processing Systems
Publisher: Kluwer Academic Publishers
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17
VLSI for video coding
October 1995
Handbook of visual communications
Publisher: Academic Press, Inc.
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18
Integration, the VLSI Journal: Volume 5 Issue 4
December 1987
Integration, the VLSI Journal
Publisher: Elsevier Science Publishers B. V.
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19
Design and evaluation of a distributed asynchronous VLSI crossbar switch controller for a packet switched supercomputer network
July 1991
SIGARCH Computer Architecture News , Volume 19 Issue 4
Publisher: ACM
Full text available: PdfPdf (706.70 KB)
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A key component in a new high-speed prototype network, called the Multiple Crossbar Network (MCN) being developed at Los Alamos National Laboratory, is a crossbar switching core and its controller. This switching core allows for up to 32 (800 Mbit/second) ...

20
Sliceable Floorplanning by Graph Dualization
May 1995
SIAM Journal on Discrete Mathematics , Volume 8 Issue 2
Publisher: Society for Industrial and Applied Mathematics
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Previous algorithms on rectangular dual graph floorplanning generate general floorplans which include the class of nonsliceable floorplans. We examine the framework of generating sliceable floorplans using the rectangular dual graph approach and present ...


Keywords: graph dualization, planar graphs, sliceable floorplans, very large scale integration (VLSI) floorplanning
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