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Bluetooth Communication Employing Antenna Diversity
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June 2003
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ISCC '03: Proceedings of the Eighth IEEE International Symposium on Computers and Communications
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Publisher: IEEE Computer Society
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 0 |
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In order to cope with the environmental impacts onBluetooth data transmission diversity techniques wereexamined. A Bluetooth antenna diversity demonstratorwas developed. Extensive experimental investigationsdocumenting the significant improvements of ...
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2
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A Mathematical Model and Scheduling Heuristics for Satisfying Prioritized Data Requests in an Oversubscribed Communication Network
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September 2000
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IEEE Transactions on Parallel and Distributed Systems
, Volume 11 Issue 9
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Publisher: IEEE Press
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 7 |
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Abstract¿Providing up-to-date input to users' applications is an important data management problem for a distributed computing environment, where each data storage location and intermediate node may have specific data available, storage limitations, ...
Keywords: Communication network, data management, Dijkstra's multiple-source shortest-path algorithm, distributed processing, heterogeneous computing, scheduling heuristics.
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3
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Vector Processing as a Soft Processor Accelerator
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June 2009
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Transactions on Reconfigurable Technology and Systems (TRETS)
, Volume 2 Issue 2
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Publisher: ACM
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Full text available: |
Pdf
(1.39 MB)
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| Bibliometrics: Downloads (6 Weeks): 43, Downloads (12 Months): 142, Downloads (Overall): 142, Citation Count: 0 |
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Current FPGA soft processor systems use dedicated hardware modules or accelerators to speed up data-parallel applications. This work explores an alternative approach of using a soft vector processor as a general-purpose accelerator. The approach has ...
Keywords: Computer architecture, embedded processor, multimedia processing, parallelism, soft processor, vector processor
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A new pipelined systolic array-based architecture for matrix inversion in FPGAS with Kalman filter case study
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January 2006
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EURASIP Journal on Applied Signal Processing
, Volume 2006
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Publisher: Hindawi Publishing Corp.
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Full text available: |
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(838.90 KB)
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| Bibliometrics: Downloads (6 Weeks): 6, Downloads (12 Months): 30, Downloads (Overall): 102, Citation Count: 0 |
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A new pipelined systolic array-based (PSA) architecture for matrix inversion is proposed. The pipelined systolic array (PSA) architecture is suitable for FPGA implementations as it efficiently uses available resources of an FPGA. It is scalable for different ...
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6
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Scalable custom instructions identification for instruction-set extensible processors
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September 2004
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CASES '04: Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
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Publisher: ACM
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Full text available: |
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(296.63 KB)
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| Bibliometrics: Downloads (6 Weeks): 6, Downloads (12 Months): 47, Downloads (Overall): 585, Citation Count: 26 |
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Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. However, it is computationally expensive to automatically select the optimal set of custom instructions. Therefore, heuristic ...
Keywords: ASIPs, customizable processors, instruction-set extensions, subgraph enumeration algorithm
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7
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Location prediction algorithms for mobile wireless systems
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January 2003
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Wireless internet handbook
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Publisher: CRC Press, Inc.
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 4 |
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Predicting the location of a mobile wireless user is an inherently interesting and challenging problem. Location prediction has received increasing interest over the past decade, driven by applications in location management, call admission control, ...
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8
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New approach on power efficiency of a RISC processor
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August 2008
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AIC'08: Proceedings of the 8th conference on Applied informatics and communications
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Publisher: World Scientific and Engineering Academy and Society (WSEAS)
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 0 |
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Most often, for a digital electronic device, the consumed power is indicated as an average value without explicitly expressing the functional conditions under which this power was measured. This is also true for microprocessors. For a large part of the ...
Keywords: RISC processors, energetic efficiency, leakage currents, power consumption
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9
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On Self-Routing in Benes and Shuffle-Exchange Networks
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September 1991
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IEEE Transactions on Computers
, Volume 40 Issue 9
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Publisher: IEEE Computer Society
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 6 |
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The authors present self-routing algorithms for realizing the class of linear permutations in various multistage networks such as Benes and 2n-stage shuffle-exchange. Linear permutations are useful in providing fast access of data arrays. In the first ...
Keywords: Benes networks, interconnection networks, multiprocessor interconnection networks., network self-routing, self-routing algorithms, shuffle-exchange networks
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10
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On improving the performance of IEEE 802.11 with relay-enabled PCF
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August 2004
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Mobile Networks and Applications
, Volume 9 Issue 4
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Publisher: Kluwer Academic Publishers
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Full text available: |
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(594.85 KB)
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| Bibliometrics: Downloads (6 Weeks): 3, Downloads (12 Months): 39, Downloads (Overall): 586, Citation Count: 4 |
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Integrating wireless LAN (WLAN) techniques with the third generation cellular networks has become a promising way to improve the performance of wireless systems. As WLANs play an important role in such heterogeneous systems, the performance of WLANs ...
Keywords: IEEE 802.11, media access control, rate adaptation, relay
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11
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The art of multiprocessor programming
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July 2006
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PODC '06: Proceedings of the twenty-fifth annual ACM symposium on Principles of distributed computing
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Publisher: ACM
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Full text available: |
Pdf
(27.70 KB)
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| Bibliometrics: Downloads (6 Weeks): 18, Downloads (12 Months): 183, Downloads (Overall): 786, Citation Count: 0 |
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Computer architecture is about to undergo, if not another revolution, then a vigorous shaking-up. The major chip manufacturers have, for the time being, simply given up trying to make processors run faster. Instead, they have recently started shipping ...
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Computer architecture simulation models
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June 2006
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ITICSE '06: Proceedings of the 11th annual SIGCSE conference on Innovation and technology in computer science education
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Publisher: ACM
Request Permissions
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Full text available: |
Pdf
(94.12 KB)
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| Bibliometrics: Downloads (6 Weeks): 8, Downloads (12 Months): 42, Downloads (Overall): 175, Citation Count: 0 |
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Simulation models of a variety of computer architectures have been created using HASE, a Hierarchical Computer Architecture design and Simulation Environment. Some of these models were previously available as applets but using the models directly in ...
Keywords: computer architecture simulation
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Also published in: |
| September 2006 |
SIGCSE Bulletin |
Volume 38 Issue 3 |
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13
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Performance evaluation of combining data migration and method migration in object database environments
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January 2002
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ADC '02: Proceedings of the 13th Australasian database conference - Volume 5
, Volume 5
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Publisher: Australian Computer Society, Inc.
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Full text available: |
Pdf
(796.12 KB)
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| Bibliometrics: Downloads (6 Weeks): 1, Downloads (12 Months): 18, Downloads (Overall): 431, Citation Count: 0 |
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In this paper, we discuss efficient combinations of data migration processing and method migration processing in object database environments. When we have multiple servers and clients, it is practical to decide at a client which of the two ways should ...
Keywords: data migration, distributed methods, distributed processing, method migration, object databases, performance evaluation
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Also published in: |
| January 2002 |
Australian Computer Science Communications |
Volume 24 Issue 2 |
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14
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Non-contiguous processor allocation algorithms for distributed memory multicomputers
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December 1994
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Supercomputing '94: Proceedings of the 1994 conference on Supercomputing
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Publisher: IEEE Computer Society Press
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Full text available: |
Pdf
(1.01 MB)
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| Bibliometrics: Downloads (6 Weeks): 3, Downloads (12 Months): 5, Downloads (Overall): 184, Citation Count: 6 |
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Current processor allocation techniques for highly parallel systems have thus far been restricted to contiguous allocation strategies for which performance suffers significantly due to the inherent problem of fragmentation. We are investigating processor ...
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15
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The RP3 program visualization environment
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September 1991
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IBM Journal of Research and Development
, Volume 35 Issue 5-6
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Publisher: IBM Corp.
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 9 |
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Hierarchical FPGA Clustering Based on a Multilevel Partitioning Approach to Improve Routability and Reduce Power Dissapation
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September 2005
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RECONFIG '05: Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05) on Reconfigurable Computing and FPGAs
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Publisher: IEEE Computer Society
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 0 |
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We present a routability-driven top-down clustering technique for area and power reduction in clustered FPGAs. This technique is based on a multilevel partitioning approach. It leads to better device utilization, savings in area, and reduction in power ...
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17
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SP2 system architecture
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April 1995
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IBM Systems Journal
, Volume 34 Issue 2
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Publisher: IBM Corp.
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 38 |
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Software Processing Performance in Network Processors
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February 2004
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DATE '04: Proceedings of the conference on Design, automation and test in Europe - Volume 3
, Volume 3
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Publisher: IEEE Computer Society
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Full text available: |
Pdf
(126.22 KB)
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| Bibliometrics: Downloads (6 Weeks): 0, Downloads (12 Months): 14, Downloads (Overall): 73, Citation Count: 1 |
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To meet the demand for higher performance, flexibility, and economy in today's state-of-the-art networks, an alternative to the ASICs that traditionally were used to implement packet-processing functions in hardware, called network processors (NPs), ...
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Combining Program Recovery, Auto-Parallelisation and Locality Analysis for C Programs on Multi-Processor Embedded Systems
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September 2003
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PACT '03: Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques
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Publisher: IEEE Computer Society
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 2 |
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This paper develops a complete auto-parallelisation approach for multiple-address space digital signal processors (DSPs). It combines a pointer conversion technique with a new modulo elimination transformation. This is followed by a combined parallelisation ...
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