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Results 1 - 20 of 1,397
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1
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Towards support for design description languages in EDA framework
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November 1994
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ICCAD '94: Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
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Publisher: IEEE Computer Society Press
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Full text available: |
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(666.28 KB)
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| Bibliometrics: Downloads (6 Weeks): 1, Downloads (12 Months): 5, Downloads (Overall): 76, Citation Count: 1 |
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We report on a new framework service for design tool encapsulation, based on an information model for design management. The new service uses generated language processors that perform import and export of design files to and from a design management ...
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2
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Design space exploration of an open-source, IP-reusable, scalable floating-point engine for embedded applications
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December 2008
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Journal of Systems Architecture: the EUROMICRO Journal
, Volume 54 Issue 12
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Publisher: Elsevier North-Holland, Inc.
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 0 |
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This paper describes an open-source and highly scalable floating-point unit (FPU) for embedded systems. Our FPU is fast and efficient, due to the high parallelism of its architecture: the functional units inside the datapath can operate in parallel and ...
Keywords: Coprocessor, Embedded, FPU, Floating-point, VHDL
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Analyzing multiple register sets
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June 1985
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ISCA '85: Proceedings of the 12th annual international symposium on Computer architecture
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Publisher: ACM
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Full text available: |
Pdf
(758.32 KB)
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| Bibliometrics: Downloads (6 Weeks): 7, Downloads (12 Months): 18, Downloads (Overall): 162, Citation Count: 6 |
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Also published in: |
| June 1985 |
SIGARCH Computer Architecture News |
Volume 13 Issue 3 |
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6
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An iterative improvement algorithm for low power data path synthesis
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December 1995
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ICCAD '95: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
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Publisher: IEEE Computer Society
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| Bibliometrics: Downloads (6 Weeks): 5, Downloads (12 Months): 26, Downloads (Overall): 205, Citation Count: 18 |
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We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects of several behavioral synthesis tasks like module selection, clock selection, ...
Keywords: Behavioral synthesis, Low power VLSI design, Power consumption
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7
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An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits
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March 2001
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IEEE Transactions on Computers
, Volume 50 Issue 3
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Publisher: IEEE Computer Society
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 7 |
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Abstract¿Carry-save-adder (CSA) is one of the most widely used components for fast arithmetic in industry. This paper provides a solution to the problem of finding an optimal-timing allocation of CSAs in arithmetic circuits. Namely, we present a polynomial ...
Keywords: Carry-save-addition, arithmetic circuits, VLSI.
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8
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A study of 80x86/80x87 floating-point execution
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December 1992
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SIGSMALL/PC Notes
, Volume 18 Issue 3-4
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Publisher: ACM
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Full text available: |
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(436.51 KB)
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| Bibliometrics: Downloads (6 Weeks): 2, Downloads (12 Months): 9, Downloads (Overall): 183, Citation Count: 0 |
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The evolution of a processor architecture must include enhancements to both the fixed and floating-point units. To increase overall performance, architectural and implementation performance improvements to the floating-point unit must keep pace with ...
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10
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Fundamental principles of modeling timing in hardware description languages
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May 2001
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Journal of Systems Architecture: the EUROMICRO Journal
, Volume 47 Issue 5
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Publisher: Elsevier North-Holland, Inc.
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 0 |
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Keywords: ADLIB-SABLE, HDLs, VHDL, VLSI systems, digital systems, events, hardware systems, modeling, simulation, timing, verilog
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11
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12
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Behavioral simulation for analog system design verification
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September 1995
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, Volume 3 Issue 3
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Publisher: IEEE Educational Activities Department
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 3 |
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13
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14
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Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis
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October 2005
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ICCD '05: Proceedings of the 2005 International Conference on Computer Design
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Publisher: IEEE Computer Society
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 1 |
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Abstract: Power consumption in datapath modules due to redundant switching is an important design concern for high-performance applications. Operand isolation schemes are adopted to reduce redundant switching in datapaths. However, they incur considerable ...
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16
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A SAT-based procedure for verifying finite state machines in ACL2
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August 2006
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ACL2 '06: Proceedings of the sixth international workshop on the ACL2 theorem prover and its applications
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Publisher: ACM
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Full text available: |
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(272.70 KB)
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| Bibliometrics: Downloads (6 Weeks): 0, Downloads (12 Months): 8, Downloads (Overall): 56, Citation Count: 0 |
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We describe a new procedure for verifying ACL2 properties about finite state machines (FSMs) using satisfiability (SAT) solving. We present an algorithm for converting ACL2 conjectures into conjunctive normal form (CNF), which we then output and check ...
Keywords: ACL2, hardware verification, satisfiability solving, theorem proving
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17
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SystemVerilog implicit port enhancements accelerate system design & verification
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June 2008
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DAC '08: Proceedings of the 45th annual Design Automation Conference
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Publisher: ACM
 Request Permissions
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Full text available: |
Pdf
(771.96 KB)
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| Bibliometrics: Downloads (6 Weeks): 8, Downloads (12 Months): 32, Downloads (Overall): 43, Citation Count: 0 |
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The IEEE Std 1800-2005 SystemVerilog Standard added new implicit port instantiation enhancements that help accelerate top-level composition of large ASIC & FPGA Designs. This paper details the new .* and .name implicit port instantiation capabilities, ...
Keywords: .*, .name, SystemVerilog, Verilog, Verilog EMACS mode, implicit ports, instantiation
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18
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19
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Hardware support for efficient execution of Ada tasking
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January 1988
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Proceedings of the Twenty-First Annual Hawaii International Conference on Architecture Track
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Publisher: IEEE Computer Society Press
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 2 |
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20
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A two-state methodology for RTL logic simulation
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June 1999
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DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference
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Publisher: ACM
Request Permissions
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Full text available: |
Pdf
(51.47 KB)
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| Bibliometrics: Downloads (6 Weeks): 7, Downloads (12 Months): 29, Downloads (Overall): 258, Citation Count: 2 |
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Keywords: 2-state, RTL, X-state, initialization, optimism, pessimism, random, simulation
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