A novel fabrication technique using electroless copper deposition has been used to produce all-copper, chip-to-substrate connections. This process replaces solder by electrolessly joining copper pillars on the chip and substrate. The electroless copper ...

In this paper we present the Segment router, a novel router design for the interconnection networks of massively parallel computers. The design decisions of the Segment router are motivated by the need to improve the network performance ...

This paper introduces the concept of what we call analog Universal Active Device (UAD), as a step forward from Operational Amplifiers and other recently proposed active devices. The model for such a device is nothing but a two port classically known as ...

This paper presents the state-of-the-art in the field of network-on-chip (NoC) benchmarking and comparison. The study identifies the mainstream approaches, how NoCs are currently evaluated, and shows which aspects have been covered and those needing ...

Several interesting topologies emerge by incorporating the third dimension in networks-on-chip (NoC). The speed and power consumption of 3-D NoC are compared to that of 2-D NoC. Physical constraints, such as the maximum number of planes that can be vertically ...

The iSCSI protocol enables accessing SCSI I/O devices over an IP network. TCP is used as a transport for SCSI I/O commands. We describe the design considerations and decisions in defining the iSCSI protocol: why we use TCP, how multiple TCP connections ...

This paper presents a realizable RLMC1 reduction algorithm for extracted interconnect circuits based on two effective approaches: RL branch reduction and RC/LCnode reduction. Our algorithm takes advantage of some structures existing extensively in interconnect ...

The waveform interpolation (WI) speech coding algorithm has been shown to be an efficient method to describe the evolution of periodic voiced components in the speech signal. However, the conventional WI coding does not provide perfect reconstruction ...

In this paper, we present a bus and memory architectures co-synthesis technique. The co-synthesis problem is formulated as an optimization problem, where scheduling, allocation, and binding of tasks are done simultaneously in order to optimize the bus ...

Cellular Infrastructure seems to be a fertile ground for new and sometimes not so new architectural ideas. Start ups as well as mature companies propose variants on software defined radio, reconfigurable architectures and dedicated chip sets. However ...

In this paper, we characterize the performance of three existing memory management techniques, namely, buddy, round-robin, and first-touch policies. With existing memory management schemes, we find several cases where requests from different processors ...

This paper proposes a scheme that captures diverse input waveformsof CMOS gates for static timing analysis. Conventionallythe latest arrival time and transition time are calculated from thetimings when a transient waveform goes across pre-determinedreference ...

Over the past decade, a pair of synchronization instructions known as LL/SC has emerged as the most suitable set of instructions to be used in the design of lock-free algorithms. However, no existing multiprocessor system supports these instructions ...