Memory speed is growing more slowly than processor speed. This means that processors must spend more and more time waiting for data to arrive from memory. One of the most effective techniques to deal with this effect is to increase the amount of in-flight ...

We analyze circuits for kernels from popular quantum computing applications, characterizing the hardware resources necessary to take ancilla preparation off the critical path. The result is a chip entirely dominated by ancilla generation circuits. To ...

We present a novel mechanism, called meeting point thread characterization, to dynamically detect critical threads in a parallel region. We define the critical thread the one with the longest completion time in the parallel region. Knowing the criticality ...

Recent works$^(1)$ show that delays introduced in the issue and bypass logic will become critical for wide issue superscalar processors. One of the proposed solutions is clustering the processor core. Clustered ...

Current software-based microarchitecture simulators are many orders of magnitude slower than the hardware they simulate. Hence, most microarchitecture design studies draw their conclusions from drastically truncated benchmark simulations that are often ...

While soft processors are increasingly common in FPGA-based embedded systems, it remains a challenge to scale their performance. We propose extending soft processor instruction sets to include support for vector processing. The resulting system ...

Power gating is usually driven by a predictive control, and frequent mispredictions can counter-productively lead to a large increase in energy consumption. This energy vulnerability could be exploited by malicious applications such as a power virus, ...

Abstract¿In this paper, we propose a new processor framework that supports dynamic optimization. The rePLay Framework embeds an optimization engine atop a high-performance execution engine. The heart of the rePLay Framework is the concept of a frame. ...

The organization and management of microprocessor storage structures (e.g., L1 caches, TLBs, etc.) is critical to the performance and energy consumption of the microprocessor. We propose and develop the first microprocessor that can dynamically allocate ...

Transient faults are expected a be a major design consideration in future microprocessors. Recent proposals for transient fault detection in processor cores have revolved around the idea of redundant threading, which involves redundant execution of a ...

Conventionally, microarchitecture designs are mainly guided by the maximum throughput (measured as IPC) and fail to evaluate the impact of architectural decisions on the physical design, and in particular, the impact on the interconnects. In this paper, ...

In this article we propose techniques that enable efficient exploration of the 3D design space, where each logical block can span more than one silicon layer. Fine-grain 3D integration provides reduced intrablock wire delay as well as improved power ...

This paper describes the implementation of the Pentium processor (73590,815100), referred to as the Pentium processor-90/100 from now on, on a 3.3V, 0.6 micron BiNMOS process. The processor achieves significantly higher performance over the previous ...

During the recent development of a next-generation Intel processor, the project's formal verification team verified a new coherence protocol and portions of its RTL implementation against the protocol's specification within project deadlines. Typically, ...

Abstract¿Branch target buffers, or BTBs, are small caches for program branching information. Like data caches, addresses are divided into equivalence classes based on their low order bits. Unlike data caches, however, complete resolution of a single ...

Asynchronous systems are attracting the interest of a growing number of designers. However, the lack of simulation tools devoted to asynchronous microarchitectures is a gap that is not narrowed today. One of the main obstacles on the simulation of asynchronous ...

This paper discusses potential solutions to the CMOS device technology scaling at gate lengths approaching 10nm. Promising circuit and design techniques to control leakage power are described. Energy-efficient microarchitecture trends for general-purpose ...

Aggressive technology scaling is increasing the impact of soft errors on microprocessor reliability. Dynamic Voltage Frequency Scaling (DFVS) algorithms are conventionally studied from a performance per watt basis. But applying DVFS impacts reliability ...