Abstract: One of the most sought after software innovation of this decade is the construction of systems using off-the-shelf-workstations that actually deliver and even surpass, the power and reliability of supercomputers. Using completely novel techniques: ...

The paper gives the details of VLAN technology and explains not only how it works, but also explains the different types of VLANs and where they should be in a network. Some real world networks and some of the common problems associated with those traditional ...

Abstract: This paper details research on systems which use a small set of objects to visualize event-based data from a number of potential domains, including programming languages. Empirical research suggests that user understanding of visualizations ...

Minimum-area very large scale integration (VLSI) networks have been proposed for sorting N elements in O(log,N) time. However, most of such networks proposed have complex structures, and no explicit network construction is given in others. New designs ...

Contact graphs of isothetic rectangles unify many concepts from applications including VLSI and architectural design, computational geometry, and GIS. Minimizing the area of their corresponding rectangular layouts is a key problem. We study the ...

Several studies have been conducted on blocked data layouts, in conjunction with loop tiling to improve locality of references. In this paper, we further reduce cache misses, restructuring the memory layout of multi-dimensional arrays, so that array ...

It is well known that graphical representations could be very helpful to browse in graph structured information. But this promising approach requires the capability of an automatic layout system because the tedious and time consuming task of a manual ...

Most computer users are accustomed to the QWERTY keyboard layout. This study was started from the hypothesis that a user's skill in a QWERTY keyboard may be transferred to a 3x4 keypad environment. In order to test the hypothesis, we designed an experiment ...

We describe the design, implementation, and performance of a new parallel sparse Cholesky factorization code. The code uses a multifrontal factorization strategy. Operations on small dense submatrices are performed using new dense matrix subroutines ...

Abstract¿We present an abstraction, called data relation vectors, to improve the data access characteristics and memory layouts in regular computations. The key idea is to define a relation between the data elements accessed by close-by iterations and ...

The tremendous growth of system memories has increased the capacities and capabilities of memory-resident embedded databases, yet current embedded databases need to be tuned in order to take advantage of new memory technologies. In this paper, we study ...

In this paper, we propose an algorithm for partitioning parameterized orthogonal polygons into rectangles. The algorithm is based on the plane-sweep technique and can be used for partitioning polygons which contain holes. The input to the algorithm consists ...

Efficient use of the memory hierarchy is essential for good performance due to the ever increasing gap between processor and memory speed. Program transformations such as loop tiling have been shown to be an effective approach to improving locality and ...

A new methodology for the layout design of several classes of useful VLSI structures is proposed. The approach produces a structured layout for commonly found computation structures, using regular elements called layout slices. Algorithms for optimal ...

Presents a global approach to solve the three-layer wirability problem for knock-knee layouts. In general, the problem is NP-complete. Only for very restricted classes of layouts polynomial three-layer wiring algorithms are known up to now. The authors ...

An algorithm for partitioning parameterized 45-degree polygons into parameterized trapezoids is proposed in this article. The algorithm is based on the plane-sweep technique and can handle polygons with complicated constraints. The input to the algorithm ...

We present a novel LOD (level-of-detail) algorithm to accelerate ray tracing of massive models. Our approach computes drastic simplifications of the model and the LODs are well integrated with the kd-tree data structure. We introduce a simple and efficient ...

A Gallium Arsenide automated layout generation system (OLYMPO) for SSI, MSI and LSI circuits used in GaAs VLSI design has been developed. We introduce a full-custom layout style, called RN-based cell model, that it is suited to generate low self-inductance ...