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Found 7 of 1,394,228
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1
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Multiprocessor validation of the Pentium Pro microprocessor
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February 1996
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COMPCON '96: Proceedings of the 41st IEEE International Computer Conference
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Publisher: IEEE Computer Society
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 2 |
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The Pentium Pro microprocessor, the latest generation Intel Architecture processor, was designed to be used glue-lessly in multiprocessor (MP) systems. The processor and its associated chipset provide all the features that an MP system requires. Our ...
Keywords: Intel Architecture processor, Pentium Pro microprocessor, chipset, computer architecture, computer testing, formal verification, hardware scalability, high-level system models, integrated circuit testing, microbenchmarks, microprocessor chips, multiprocessing systems, multiprocessor systems, multiprocessor validation, performance, performance evaluation, self-checking test templates, test methodology
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2
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The Blackford Northbridge Chipset for the Intel 5000
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March 2007
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IEEE Micro
, Volume 27 Issue 2
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Publisher: IEEE Computer Society Press
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 0 |
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The Intel 5000 is a shared-memory, symmetric dual-processor system based on the energy-efficient, high-performance Intel Core 2 dual- and quad-core processors. A key component is the northbridge, which interconnects processor, memory, and I/O interfaces. ...
Keywords: platform architecture, shared memory, dual-processor system, northbridge chipset, low-power design, I/O bridges, FB-DIMM memory technology
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3
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Comprehensive Approach to High-Performance Server Chipset Debug
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May 2009
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IEEE Design & Test
, Volume 26 Issue 3
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Publisher: IEEE Computer Society Press
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 0 |
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This article describes a comprehensive approach for silicon debug of a server chipset that includes a high-performance, third-generation chip-multithreaded (CMT) Sparc microprocessor. Efficiently debugging the chipset required a combination of debug ...
Keywords: verification, test generation, design and test, multithreaded processors, server chipset, debug, SerDes, CMT Sparc microprocessor, RAS
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4
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Power phase variation in a commercial server workload
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October 2006
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ISLPED '06: Proceedings of the 2006 international symposium on Low power electronics and design
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Publisher: ACM
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Full text available: |
 Pdf
(612.68 KB)
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| Bibliometrics: Downloads (6 Weeks): 7, Downloads (12 Months): 27, Downloads (Overall): 114, Citation Count: 1 |
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Many techniques have been developed for adaptive power management of computing systems. These techniques rely on the presence of varying power phases to detect opportunities for adaptation. However, little information is available regarding the extent ...
Keywords: chipset, commercial workload characterization, disk, memory, microprocessor, power, program phase
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5
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The performance and PowerPC Platform specification implementation of the MPC106 chipset
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February 1996
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COMPCON '96: Proceedings of the 41st IEEE International Computer Conference
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Publisher: IEEE Computer Society
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 0 |
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The MPC106 provides a PowerPC Platform specification compliant bridge between the family of PowerPC Microprocessors and the PCI bus. The MPC106's PCI support will allow system designers to rapidly design systems using peripherals already designed for ...
Keywords: CHRP, Common Hardware Reference Platform, DRAM, MPC106 chipset, Motorola products, PowerPC Microprocessors, PowerPC Platform specification implementation, ROM, high-performance memory controller, industry standard interfaces, microprocessor chips, performance evaluation, personal computer hardware environment, secondary cache control, system level support
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6
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Pentium Pro processor workstation/server PCI Chipset
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February 1996
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COMPCON '96: Proceedings of the 41st IEEE International Computer Conference
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Publisher: IEEE Computer Society
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 2 |
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The 82450GX PCI Chipset provides a high performance memory subsystem and PCI bridge solution for workstation and server Pentium Pro processor based systems. This paper describes the architecture, performance, and feature set of the 82450GX.
Keywords: 82450GX, DRAM, DRAM chips, PCI Chipset, PCI bridge, Pentium Pro processor, computer architecture, feature set, high performance memory subsystem, microprocessor chips, performance, performance evaluation, storage management chips, system buses, workstation, workstations
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7
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A prototype chipset for a large scaleable ATM switching node
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March 1997
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GLS '97: Proceedings of the 7th Great Lakes Symposium on VLSI
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Publisher: IEEE Computer Society
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 0 |
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This paper presents a chipset for a 16/spl times/16 switching node for the distributed banyan network. This chipset enables the use of a larger and much more efficient switching node than was previously available. Very high performance is required of ...
Keywords: 1 micron, CMOS IC, CMOS digital integrated circuits, banyan network, dynamic logic, large scaleable ATM switching node, packet headers storage, prototype chipset, register file, static logic
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