The mixed static-dynamic circuits are widely used to design high-performance circuits (e.g. ALU, communication circuit etc), among them the most famous one is the True Single-PhaseClocked (TSPC) dynamic circuits. The TSPC is often used to design high-speed ...

Increasing demand for high-speed interchip interconnects requires faster links that consume less power. The Shannon limit for the capacity of these links is at least an order of magnitude higher than the data rate of the current state-of-the-art designs. ...

Abstract¿The paper presents an efficient scheme to compress and decompress in parallel deterministic test patterns for circuits with multiple scan chains. It employs a boundary-scan-based environment for high quality testing with flexible trade-offs ...

We present a methodology for microarchitectural customization of embedded processors by exploiting application information, thus attaining the twin benefits of processor standardization and application-specific customization. Such powerful techniques ...

With the advance in semiconductor technology we are able to pack more and more devices on a single chip [5]. However, the threat comes from the long interconnect wires [6] whose delays dominate in deep-submicron (DSM) CMOS. To handle the increased latency ...

The context for partitioning in physical design is dominated by two concerns: top-down design and the focus on spatial embedding. The role of partitioning is exactly that of a facilitator of divide-and-conquer metaheuristics for floorplanning, timing ...

An analytical two-dimensional capacitance-voltage model for AlGaN/GaN high electron mobility transistor (HEMTs) is developed, which is valid from a linear to saturation region. The gate source and gate drain capacitances are calculated for 120nm gate ...

A flexible test architecture for embedded cores and all interconnects in a System-on Chip (SOC) is presented. It targets core testing parallelism and reduced test application time by using, as much as possible, existing core interconnects to form TAM ...

Modern Systems-on-Chip (SoCs) allow integrating many different functional cores in the same piece of silicon. Their test requires to take fast decisions in the selection of structures and strategies at different stages of the design flow: early computation ...

This paper introduces self-tuning identification free PSD control algorithm and its new modification. On the basis of detailed analysis of algorithm function made by simulation experiments, several modification of original algorithm have been proposed, ...

The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. These small delay defects might be activated on longer paths during functional ...

Shrinking process geometries and frequency scaling give rise to an increasing number of interconnects that require multiple clock cycles. This paper explores efficient techniques to insert flip-flops and latches to meet pre-determined latency and margin ...

This paper presents the state-of-the-art in the field of network-on-chip (NoC) benchmarking and comparison. The study identifies the mainstream approaches, how NoCs are currently evaluated, and shows which aspects have been covered and those needing ...

Several interesting topologies emerge by incorporating the third dimension in networks-on-chip (NoC). The speed and power consumption of 3-D NoC are compared to that of 2-D NoC. Physical constraints, such as the maximum number of planes that can be vertically ...

Editor's note: What would it take to reduce speed binning's dependency on functional testing? One answer is a structural at-speed test approach that can achieve the same effectiveness as functional testing. The authors of this article offer a formula ...