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Results 1 - 20 of 9,674
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Design Scan Test Strategy for Single Phase Dynamic Circuits
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November 2003
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DFT '03: Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
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Publisher: IEEE Computer Society
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 0 |
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The mixed static-dynamic circuits are widely used to design high-performance circuits (e.g. ALU, communication circuit etc), among them the most famous one is the True Single-PhaseClocked (TSPC) dynamic circuits. The TSPC is often used to design high-speed ...
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2
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Three-dimensional integrated circuit layout
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January 1992
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Three-dimensional integrated circuit layout
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Publisher: Cambridge University Press
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 1 |
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ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction
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June 2008
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DAC '08: Proceedings of the 45th annual Design Automation Conference
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Publisher: ACM
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Full text available: |
 Pdf
(609.13 KB)
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| Bibliometrics: Downloads (6 Weeks): 3, Downloads (12 Months): 43, Downloads (Overall): 60, Citation Count: 1 |
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In this paper, we present ELIAD, an efficient lithography aware detailed router to optimize silicon image after optical proximity correction (OPC) in a correct-by-construction manner. We first propose a compact post-OPC litho-metric for a detailed router ...
Keywords: OPC, VLSI, lithography, manufacturability, routing
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5
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Automatic generation and characterization of CMOS polycells
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June 1981
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DAC '81: Proceedings of the 18th Design Automation Conference
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Publisher: IEEE Press
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Full text available: |
Pdf
(385.27 KB)
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| Bibliometrics: Downloads (6 Weeks): 0, Downloads (12 Months): 2, Downloads (Overall): 56, Citation Count: 0 |
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With increasing complexity and size of integrated circuits, computer aids for layout and simulation have begun to play an ever-increasing role. An approach to take advantage of these aids is the polycell design approach. However, thus far, manual procedures ...
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6
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Futures for partitioning in physical design (tutorial)
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April 1998
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ISPD '98: Proceedings of the 1998 international symposium on Physical design
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Publisher: ACM
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Full text available: |
Pdf
(646.11 KB)
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| Bibliometrics: Downloads (6 Weeks): 6, Downloads (12 Months): 19, Downloads (Overall): 187, Citation Count: 2 |
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The context for partitioning in physical design is dominated by two concerns: top-down design and the focus on spatial embedding. The role of partitioning is exactly that of a facilitator of divide-and-conquer metaheuristics for floorplanning, timing ...
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7
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Partial and Dynamic Reconfiguration of FPGAs: a top down design methodology for an automatic implementation
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March 2006
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ISVLSI '06: Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
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Publisher: IEEE Computer Society
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 3 |
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Dynamic and partial reconfiguration of FPGAs enables systems to adapt to changing demands. This paper concentrates on how to take into account specificities of partially reconfigurable components during the high level Adequation Algorithm Architecture ...
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8
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9
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Electronic design automation using a unified optimization framework
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December 2008
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Mathematics and Computers in Simulation
, Volume 79 Issue 4
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Publisher: Elsevier Science Publishers B. V.
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 0 |
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This work proposes an object-oriented unified optimization framework (UOF) for general problem optimization. Based on biological inspired techniques, numerical deterministic methods, and C++ objective design, the UOF itself has significant potential ...
Keywords: Biological inspired techniques, Design automation, Deterministic method, Simulation-based optimization
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10
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Clocking Optimization and Distribution in Digital Systemswith Scheduled Skews
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July 1997
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Journal of VLSI Signal Processing Systems
, Volume 16 Issue 2/3
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Publisher: Kluwer Academic Publishers
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 0 |
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System performance can be improved by employing scheduled skews at
flip-flops. This optimization technique is called skewed-clock
optimization and has been successfully used in memory designs to
achieve high operating frequencies. There are two important ...
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11
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12
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DECOR—tightly integrated Design Control and Observation
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December 1992
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ICCAD '92: 1992 IEEE/ACM international conference proceedings on Computer-aided design
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Publisher: IEEE Computer Society Press
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 0 |
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13
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On Self-Routing in Benes and Shuffle-Exchange Networks
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September 1991
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IEEE Transactions on Computers
, Volume 40 Issue 9
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Publisher: IEEE Computer Society
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 6 |
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The authors present self-routing algorithms for realizing the class of linear permutations in various multistage networks such as Benes and 2n-stage shuffle-exchange. Linear permutations are useful in providing fast access of data arrays. In the first ...
Keywords: Benes networks, interconnection networks, multiprocessor interconnection networks., network self-routing, self-routing algorithms, shuffle-exchange networks
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14
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3-D topologies for networks-on-chip
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October 2007
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, Volume 15 Issue 10
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Publisher: IEEE Educational Activities Department
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 3 |
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Several interesting topologies emerge by incorporating the third dimension in networks-on-chip (NoC). The speed and power consumption of 3-D NoC are compared to that of 2-D NoC. Physical constraints, such as the maximum number of planes that can be vertically ...
Keywords: 3-D circuits, 3-D integrated circuits (ICs), 3-D integration, networks-on-chip (NoC), topologies
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15
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Minimal area sizing of power supply nets in VLSI circuits
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January 1991
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Journal of Information Processing and Cybernetics
, Volume 26 Issue 11-12
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Publisher: Akademie-Verlag GmbH
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 0 |
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16
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Speed Binning with Path Delay Test in 150-nm Technology
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September 2003
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IEEE Design & Test
, Volume 20 Issue 5
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Publisher: IEEE Computer Society Press
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 11 |
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Editor's note: What would it take to reduce speed binning's dependency on functional testing? One answer is a structural at-speed test approach that can achieve the same effectiveness as functional testing. The authors of this article offer a formula ...
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20
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Speeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary
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May 2007
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VTS '07: Proceedings of the 25th IEEE VLSI Test Symmposium
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Publisher: IEEE Computer Society
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Downloads (Overall): n/a, Citation Count: 1 |
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In this paper we present a new technique to speed up the effect-cause defect diagnosis by using a dictionary of very small size. In the proposed method, a dictionary of small size is used to reduce the number of events (gate evaluations) during the simulation ...
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