The Convex C220 and C240 supercomputers are a family of 64-bit multiprocessors, tightly coupled through a shared main memory. Each processor contains an integrated vector processor. All processor features, including the vector processor, are controlled ...

We have investigated a self-assembly process for patterning epitaxial CoSi2 nanowires using local oxidation of silicides (LOCOSI). This involves single-crystalline, epitaxial CoSi2 grown on Si(100) by molecular beam allotaxy (MBA). ...

The mixed static-dynamic circuits are widely used to design high-performance circuits (e.g. ALU, communication circuit etc), among them the most famous one is the True Single-PhaseClocked (TSPC) dynamic circuits. The TSPC is often used to design high-speed ...

Magnetic Random Access Memory (MRAM) has been considered as a promising memory technology due to many attractive properties. Integrating MRAM with CMOS logic may incur extra manufacture cost, due to its hybrid magnetic-CMOS fabrication process. Stacking ...

As new Internet technologies emerge, the ability to do full regular expression pattern matching on network packets to support these new technologies is becoming increasingly important. Current technologies that can benefit from high-speed pattern matching ...

Abstract¿The paper presents an efficient scheme to compress and decompress in parallel deterministic test patterns for circuits with multiple scan chains. It employs a boundary-scan-based environment for high quality testing with flexible trade-offs ...

In this paper, an adaptive Linear Quadratic Regulator (LQR) with Repetitive (RP) control is applied to Uninterruptible Power Supply (UPS) systems. The RP controller with forgetting parameters is used to attenuate the effects of periodic disturbances. ...

A new pipelined systolic array-based (PSA) architecture for matrix inversion is proposed. The pipelined systolic array (PSA) architecture is suitable for FPGA implementations as it efficiently uses available resources of an FPGA. It is scalable for different ...

In this paper, we present ELIAD, an efficient lithography aware detailed router to optimize silicon image after optical proximity correction (OPC) in a correct-by-construction manner. We first propose a compact post-OPC litho-metric for a detailed router ...

With increasing complexity and size of integrated circuits, computer aids for layout and simulation have begun to play an ever-increasing role. An approach to take advantage of these aids is the polycell design approach. However, thus far, manual procedures ...

We demonstrate a novel Opto-VLSI tunable fiber ring laser structure in which an Opto-VLSI processor driven by steering phase holograms dynamically selects the lasing wavelengths. A proof-of-concept tunable fiber ring laser which has a wavelength tuning ...

With the advance in semiconductor technology we are able to pack more and more devices on a single chip [5]. However, the threat comes from the long interconnect wires [6] whose delays dominate in deep-submicron (DSM) CMOS. To handle the increased latency ...

The context for partitioning in physical design is dominated by two concerns: top-down design and the focus on spatial embedding. The role of partitioning is exactly that of a facilitator of divide-and-conquer metaheuristics for floorplanning, timing ...

Dynamic and partial reconfiguration of FPGAs enables systems to adapt to changing demands. This paper concentrates on how to take into account specificities of partially reconfigurable components during the high level Adequation Algorithm Architecture ...