The Convex C220 and C240 supercomputers are a family of 64-bit multiprocessors, tightly coupled through a shared main memory. Each processor contains an integrated vector processor. All processor features, including the vector processor, are controlled ...

Increasing demand for high-speed interchip interconnects requires faster links that consume less power. The Shannon limit for the capacity of these links is at least an order of magnitude higher than the data rate of the current state-of-the-art designs. ...

One of the fundamental properties of a graph is the number of distinct eigenvalues of its adjacency or Laplace matrix. Determining this number is of theoretical interest as well as of practical impact. Sparse graphs with small spectra exhibit excellent ...

With the advance in semiconductor technology we are able to pack more and more devices on a single chip [5]. However, the threat comes from the long interconnect wires [6] whose delays dominate in deep-submicron (DSM) CMOS. To handle the increased latency ...

A novel fabrication technique using electroless copper deposition has been used to produce all-copper, chip-to-substrate connections. This process replaces solder by electrolessly joining copper pillars on the chip and substrate. The electroless copper ...

In this paper we present the Segment router, a novel router design for the interconnection networks of massively parallel computers. The design decisions of the Segment router are motivated by the need to improve the network performance ...

This paper introduces the concept of what we call analog Universal Active Device (UAD), as a step forward from Operational Amplifiers and other recently proposed active devices. The model for such a device is nothing but a two port classically known as ...

This paper presents the state-of-the-art in the field of network-on-chip (NoC) benchmarking and comparison. The study identifies the mainstream approaches, how NoCs are currently evaluated, and shows which aspects have been covered and those needing ...

Several interesting topologies emerge by incorporating the third dimension in networks-on-chip (NoC). The speed and power consumption of 3-D NoC are compared to that of 2-D NoC. Physical constraints, such as the maximum number of planes that can be vertically ...

We address issues and parameters related to providing increased interoperability between the IP and the optical layer such that next generation intelligent optical platforms for wavelength switched cross-connected topologies are enabled.

The software-defined-radio concept received increasing attention due to necessity of multi-mode/multi-system capable terminals for next generation communication systems. This paper summarizes the requirements of a multi-mode compliant digital-front-end ...

In this paper we give precise solutions to problems posed by Wang, An, Pan, Wang and Qu and by Hsieh, Lin and Huang. In particular, we show that Qnk is bipanconnected and edge-bipancyclic, when k ≥ 3 and n ≥ 2, and we also show that when ...

The iSCSI protocol enables accessing SCSI I/O devices over an IP network. TCP is used as a transport for SCSI I/O commands. We describe the design considerations and decisions in defining the iSCSI protocol: why we use TCP, how multiple TCP connections ...