Volume rendering has great potential for parallelization due to the tremendous number of computations necessary. Besides the enormous computational power needed, the memory interface is usually of crucial importance and frequently the bottleneck.This ...

A two-port memory contains two duplicated sets of address decoders, which operate independently. Testing such memories requires the use of single-port tests as well as special two-port tests; the test strategy determines which tests have to be used. ...

This paper presents a complete electrical analysis of Address decoder Delay Faults "ADFs” caused by resistive opens in RAMs. A classification between inter and intragate opens is made. A systematic way is introduced to explore the space of possible ...

In this paper is proposed a technique to integrate and simulate a dynamic memory in a multiprocessor framework based on C/C++/SystemC. Using host machine's memory management capabilities, dynamic data processing is supported without compromising speed ...

The objective of this paper is to propose a BIST scheme enabling the test of delay faults in all the Look-Up Tables (LUTs) of FPGA SRAMs, in a Manufacturing context. The BIST scheme does not consume any area overhead and can be removed from the device ...

Transparent built-in self test (BIST) schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric transparent BIST skips the signature prediction phase required in traditional transparent BIST schemes, achieving ...

This paper describes the NPSE, a high-performance SRAM-based network packet search engine which has the primary application of supporting IPv4 and IPv6 forwarding. It is based on a high-speed hardware implementation of a tree-based storage and retrieval ...

This paper describes Maps, a compiler managed memory system for Raw architectures. Traditional processors for sequential programs maintain the abstraction of a unified memory by using a single centralized memory system. This implementation leads to the ...

A multilevel level cell (MLC) technique for flash memories reduces the bit cost and enhances the memory density. However, it is difficult to get a required sensing margin for MLC due to the need for the tight threshold voltage control. We present a novel ...

In this paper, we provide an analytical framework tostudy the inter-cell and intra-cell bit-line coupling when itis superimposed with the ground bounce effect and showhow those noises impair the performance of SRAM. Theimpact of noises is expressed in ...

We introduce a new Static Random Access Memory (SRAM) cell that offers high stability and reduces gate leakage power in caches while maintaining low access latency. Our design exploits the strong bias towards zero at the bit level exhibited by the memory ...

As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric ...

This paper presents a novel parallel memory architecture for multimedia computers. Applying a configurable or programmable addressing circuitry capable of parallel memory accesses, the memory management of multimedia applications can be enhanced. Necessary ...

This paper presents a word-line voltage generator for multilevel (ML) Flash memory programming. The required voltages are provided by a regulator supplied by an on-chip charge-pump voltage multiplier. A feedback loop including a digitally programmable ...

The Semiconductor Research Corp. is one of the few organizations to get fierce competitors like Intel, Motorola, and IBM to the same table, let alone cooperate. And it has also wrangled money- $37 million annually-from these companies and others. With ...

This paper analyses the effects of Single Event Upsets in an SRAM-based FPGA, with special emphasis for the transient faults affecting the configuration memory. Two approaches are combined: from one side, by exploiting the available information and tools ...

This paper explores the Built-In Self Test (BIST) concepts to test the configurable logic blocks (CLBs) of Static RAM (SRAM) based FPGAs using Java Bits (JBits). The proposed technique detects and diagnoses single and multiple stuck-at faults in the ...