A High-Speed Transceiver Architecture Implementable as Synthesizable IP Core

ABSTRACT

In this work, a synthesizable architecture for serial high speed transceiver is presented, which can be implemented on register-transfer level (RTL) with standard hardware descriptionlanguages (HDL). The proposed implementation as a soft IP macro can be synthesized applying a semi-custom design flow, widely used in industry whenever possible.Generally, the implementation of high speed transceivers is a typical domain of a full custom design style because the timing critical parts are realized by dedicated transistor level design of the PLL/DLL based architectures. Compared to this method, the design productivity can be enhanced significantly, with the usage of this soft IP macro. With the presented implementation, data rates of about 1 GBit/s can be achieved. This is certainly less compared to full custom implementations. Nevertheless, this is an appealing solution for short design time and low cost design, if the achieved data rate is sufficient. In addition, current research showthat data rates above the mentioned result can be achieved.

REFERENCES

• 1: [1] International workshop on ip-based soc design. Grenoble, November 13-14, 2003.
• 2: [2] Cao, Momtaz, and Vakilian. Oc-192 receiver in standard 0.18µm cmos. In International Solid-State Circuits Conference , 2002.
• 3: D. G. Chinnery , K. Keutzer, Closing the gap between ASIC and custom: an ASIC perspective, Proceedings of the 37th conference on Design automation, p.637-642, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337602]
• 4: Mark Horowitz , Chih-Kong Ken Yang , Stefanos Sidiropoulos, High-Speed Electrical Signaling: Overview and Limitations, IEEE Micro, v.18 n.1, p.12-24, January 1998 [doi>10.1109/40.653013]
• 5: Howard W. Johnson , Martin Graham, High-speed digital design: a handbook of black magic, Prentice-Hall, Inc., Upper Saddle River, NJ, 1993
• 6: [6] Kurisu, Fukaishi, Asazawa, Nishikawa, Nakamura, and Yotsuyanagi. Design innovations for multi-gigahertz-rate communication circuits with deep-submicron cmos technology. IEICE Trans. Electron., Special Issue on Ultra-High-Speed IC and LSI Technology, E82-C(3), 1999.
• 7: [7] Meghelli, Rylyakov, and Shan. 50 gb/s sige bicmos 4:1 multiplexer and 1:4 demultiplexer for serial communication systems. In International Solid-State Circuits Conference, 2002.
• 8: Stephen E. Rich , Matthew J. Parker , Jim Schwartz, Reducing the frequency gap between ASIC and custom designs: a custom perspective, Proceedings of the 38th conference on Design automation, p.432-437, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.378548]
• 9: Nick Richardson , Lun Bin Huang , Razak Hossain , Tommy Zounes , Naresh Soni , Julian Lewis, The iCOREtm 520 MHz synthesizable CPU core, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514080]
• 10: [10] K. Shepard, V. Narayanan, and R. Rose. Harmony: static noise analysis of deep submicron digital integrated circuits. IEEE Transactions on CAD of ICAS, 18(8), 1999.
• 11: [11] S.-J. Song, S. M. Park, and H.-J. Yoo. A 4-gb/s cmos clock and data recovery circuit using 1/8-rate clock technique. IEEE Journal of Solid-State Circuits, 38(7), July 2003.
• 12: [12] V. Stojanovic, G. Ginis, and M. A. Horowitz. Transmit preemphasis for high-speed time-division-multiplexed serial-link transceiver. In IEEE International Conference on Communications , 2002.
• 13: [13] Yang, Farjad-Rad, and Horowitz. A 0.5µm cmos 4.0-gbit/s serial link transceiver with data recovery using oversampling. IEEE Journal of Solid-State Circuits, 33(5), May 1998.
• 14: [14] A. Zolfaghari and B. Razavi. A low-power 2.4-ghz transmitter/receiver cmos ic. IEEE Journal of Solid-State Circuits, 38(2), February 2003.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.2 Design Aids
          Subjects: Automatic synthesis

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.1 Design
          Subjects: Data-path design
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Automatic synthesis

General Terms:
Design