Transaction level modeling

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Transaction level modeling: an overview

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International Symposium on Systems Synthesis archive
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis table of contents

Newport Beach, CA, USA

SESSION: Advances in system modeling table of contents

Pages: 19 - 24

Year of Publication: 2003

ISBN:1-58113-742-7

Authors

Lukai Cai	University of California, Irvine, Irvine, CA
Daniel Gajski	University of California, Irvine, Irvine, CA

Sponsor

ACM: Association for Computing Machinery

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 42, Downloads (12 Months): 207, Citation Count: 44

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

Recently, the transaction-level modeling has been widely referred to in system-level design community. However, the transaction-level models(TLMs) are not well defined and the usage of TLMs in the existing design domains, namely modeling, validation, refinement, exploration, and synthesis, is not well coordinated. This paper introduces a TLM taxonomy and compares the benefits of TLMs' use.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	Pieter van der Wolf , Erwin de Kock , Tomas Henriksson , Wido Kruijtzer , Gerben Essink, Design and programming of embedded multiprocessors: an interface-centric approach, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 08-10, 2004, Stockholm, Sweden
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	Tim Kogel , Heinrich Meyr, Heterogeneous MP-SoC: the solution to energy-efficient signal processing, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
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