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| Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints |
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Design, Automation, and Test in Europe
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Proceedings of the conference on Design, automation and test in Europe
table of contents
Page: 168
Year of Publication: 2002
ISSN:1530-1591
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Authors
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A. Azevedo
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Center for Embedded Computer Systems, University of California, Irvine, 444 Computer Science Building, Irvine
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I. Issenin
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Center for Embedded Computer Systems, University of California, Irvine, 444 Computer Science Building, Irvine
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R. Cornea
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Center for Embedded Computer Systems, University of California, Irvine, 444 Computer Science Building, Irvine
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R. Gupta
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Center for Embedded Computer Systems, University of California, Irvine, 444 Computer Science Building, Irvine
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N. Dutt
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Center for Embedded Computer Systems, University of California, Irvine, 444 Computer Science Building, Irvine
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A. Veidenbaum
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Center for Embedded Computer Systems, University of California, Irvine, 444 Computer Science Building, Irvine
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A. Nicolau
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Center for Embedded Computer Systems, University of California, Irvine, 444 Computer Science Building, Irvine
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IEEE Computer Society
Washington, DC, USA
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| Bibliometrics |
Downloads (6 Weeks): 5, Downloads (12 Months): 24, Citation Count: 28
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 ABSTRACT
Dynamic voltage scaling (DVS) is a known effectivemechanism for reducing CPU energy consumption withoutsignificant performance degradation. While a lot of workhas been done on inter-task scheduling algorithms to implementDVS under operating system control, new researchchallenges exist in intra-task DVS techniques under softwareand compiler control. In this paper we introduce anovel intra-task DVS technique under compiler control usingprogram checkpoints. Checkpoints are generated atcompile time and indicate places in the code where the processorspeed and voltage should be re-calculated. Check-pointsalso carry user-defined time constraints. Our techniquehandles multiple intra-task performance deadlinesand modulates power consumption according to a run-timepower budget. We experimented with two heuristics for adjustingthe clock frequency and voltage. For the particularbenchmark studied, one heuristic yielded 63% more energysavings than the other. With the best of the heuristics we designed,our technique resulted in 82% energy savings overthe execution of the program without employing DVS.
CITED BY 30
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Peng Yang , Paul Marchal , Chun Wong , Stefaan Himpe , Francky Catthoor , Patrick David , Johan Vounckx , Rudy Lauwereins, Managing dynamic concurrent tasks in embedded real-time multimedia systems, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan
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Saurabh Chheda , Osman Unsal , Israel Koren , C. Mani Krishna , Csaba Andras Moritz, Combining compiler and runtime IPC predictions to reduce energy in next generation architectures, Proceedings of the 1st conference on Computing frontiers, April 14-16, 2004, Ischia, Italy
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Stefan Valentin Gheorghita , Twan Basten , Henk Corporaal, Intra-task scenario-aware voltage scheduling, Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems, September 24-27, 2005, San Francisco, California, USA
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Yung-Chia Lin , Yi-Ping You , Chung-Wen Huang , Jenq Kuen Lee , Wei-Kuan Shih , Ting-Ting Hwang, Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains, The Journal of Supercomputing, v.42 n.2, p.201-223, November 2007
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Oguz Ergin , Deniz Balkan , Kanad Ghose , Dmitry Ponomarev, Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.304-315, December 04-08, 2004, Portland, Oregon
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Deniz Balkan , Joseph Sharkey , Dmitry Ponomarev , Kanad Ghose, Selective writeback: exploiting transient values for energy-efficiency and performance, Proceedings of the 2006 international symposium on Low power electronics and design, October 04-06, 2006, Tegernsee, Bavaria, Germany
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Deniz Balkan , Joseph Sharkey , Dmitry Ponomarev , Kanad Ghose, SPARTAN: speculative avoidance of register allocations to transient values for performance and energy efficiency, Proceedings of the 15th international conference on Parallel architectures and compilation techniques, September 16-20, 2006, Seattle, Washington, USA
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Sungpack Hong , Sungjoo Yoo , Hoonsang Jin , Kyu-Myung Choi , Jeong-Taek Kong , Soo-Kwan Eo, Runtime distribution-aware dynamic voltage scaling, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
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Concepción Sanz , Manuel Prieto , José Ignacio Gómez , Antonis Papanikolaou , Miguel Miranda , Francky Catthoor, Combining system scenarios and configurable memories to tolerate unpredictability, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.3, p.1-7, July 2008
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Sungpack Hong , Sungjoo Yoo , Byeong Bin , Kyu-Myung Choi , Soo-Kwan Eo , Taehwan Kim, Dynamic voltage scaling of supply and body bias exploiting software runtime distribution, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
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