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ABSTRACT

In the past decade, there has been much literature describing various cache organizations that exploit general programming idiosyncrasies to obtain maximum hit rate (the probability that a requested datum is now resident in the cache). Little, if any, has been presented to exploit: (1) the inherent dual input nature of the cache and (2) the many-datum reference type central processor instructions. No matter how high the cache hit rate is, a cache miss may impose a penalty on subsequent cache references. This penalty is the necessity of waiting until the missed requested datum is received from central memory and, possibly, for cache update. For the two cases above, the cache references following a miss do not require the information of the datum not resident in the cache, and are therefore penalized in this fashion. In this paper, a cache organization is presented that essentially eliminates this penalty. This cache organizational feature has been incorporated in a cache/memory interface subsystem design, and the design has been implemented and prototyped. An existing simple instruction set machine has verified the advantage of this feature; future, more extensive and sophisticated instruction set machines may obviously take more advantage. Prior to prototyping, simulations verified the advantage.

REFERENCES

• 1: C. J. Conti. Concepts of buffer storage, IEEE Computer Group News, 2 (March 1969).
• 2: R. M. Meade. How a cache memory enhances a computer's performance, Electronics (Jan. 1972).
• 3: K. R. Kaplan and R. O. Winder. Cache-based computer systems, IEEE Computer (March 1973).
• 4: J. Bell, D. Casasent, and C. G. Bell. An investigation of alternative cache organizations. IEEE Transactions on Computers, C-23 (April 1974).
• 5: J. H. Kroeger and R. M. Meade (of Cogar Corporation, Woppingers Fall, NY). Cache buffer memory specification.
• 6: A. V. Pohm, O. P. Agrawal, and R. N. Monroe. The cost and performance tradeoffs of buffered memories. Proceedings of the IEEE, 63 (Aug. 1973).
• 7: A. J. Smith. Sequential program prefetching in memory hierachies, IEEE Computer (Dec 1978).
• 8: G. H. Toole. Instruction lookahead and execution traffic considerations for the _____ cache design (Development division internal paper), Control Data-Canada, 1975.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.2 Design Styles
          Subjects: Cache memories

Additional Classification:
  C. Computer Systems Organization
  C.0 GENERAL
      Subjects: Instruction set design (e.g., RISC, CISC, VLIW)

General Terms:
Design