Multi-objective optimization of interconnect geometry

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Multi-objective optimization of interconnect geometry

Source

IEEE Transactions on Very Large Scale Integration (VLSI) Systems archive
Volume 11 , Issue 1 (February 2003) table of contents
Special section on system-level interconnect prediction (SLIP)

Pages: 15 - 23

Year of Publication: 2003

ISSN:1063-8210

Authors

Raymond A. Wildman	Department of Electrical and Computer Engineering, University of Delaware, Newark, DE
Joshua I. Kramer	Department of Electrical and Computer Engineering, University of Delaware, Newark, DE
Daniel S. Weile	Department of Electrical and Computer Engineering, University of Delaware, Newark, DE
Phillip Christie	Department of Electrical and Computer Engineering, University of Delaware, Newark, DE

Publisher

IEEE Educational Activities Department Piscataway, NJ, USA

Bibliometrics

Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Citation Count: 3

Additional Information:

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DOI Bookmark:	10.1109/TVLSI.2002.808460

ABSTRACT

The rapid increase in the number of wiring layers due to improved planarization and metallization techniques permits spatial resources to be traded for improved performance. Yield, power dissipation and propagation delay are all sensitive to the selection of the pitch and width of wires in each layer. As in many other engineering design problems, however, there exists no unique solution which simultaneously optimizes all aspects of system performance. The best that can be achieved is the identification of the optimal surface within the multi-objective performance space. A single design can be chosen from this list a posteriori using additional selection criteria which may depend, for example, on the specific details of the product application. This paper investigates the use of Pareto genetic algorithms to explore the extent of multi-objective optimal surfaces. The tradeoffs between yield, power-dissipation and cycle time for a benchmark netlist are examined as a function of in-plane geometry for a seven-layer interconnect.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 3

	Raymond A. Wildman , Joshua I. Kramer , Daniel S. Weile , Phillip Christie, Wire layer geometry optimization using stochastic wire sampling, Proceedings of the 2002 international workshop on System-level interconnect prediction, April 06-07, 2002, San Diego, California, USA
	Phillip Christie , José Pineda de Gyvez, Prelayout interconnect yield prediction, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.55-59, February 2003
	Amin Farmahini-Farahani , Mehdi Kamal , Sied Mehdi Fakhraie , Saeed Safari, HW/SW partitioning using discrete particle swarm, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy