| Buffered Steiner trees for difficult instances |
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International Symposium on Physical Design
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Proceedings of the 2001 international symposium on Physical design
table of contents
Sonoma, California, United States
Pages: 4 - 9
Year of Publication: 2001
ISBN:1-58113-347-2
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Authors
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C. J. Alpert
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IBM Corp., Austin, TX
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Miloš Hrkić
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University of Illinois at Chicago, EECS Dept., Chicago, IL
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J. Hu
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IBM Corp., Austin, TX
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A. B. Kahng
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University of California at San Diego, CS Dept., San Diego, CA
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J. Lillis
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University of Illinois at Chicago, EECS Dept., Chicago, IL
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B. Liu
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University of California at San Diego, CS Dept., San Diego, CA
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S. T. Quay
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IBM Corp., Austin, TX
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S. S. Sapatnekar
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University of Minnesota, ECE Dept.
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A. J. Sullivan
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IBM Corp., Austin, TX
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P. Villarrubia
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IBM Corp., Austin, TX
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Downloads (6 Weeks): 1, Downloads (12 Months): 13, Citation Count: 11
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ABSTRACT
Buffer insertion has become an increasingly critical optimization in high performance design. The problem of finding a delay-optimal buffered Steiner tree has been an active area of research, and excellent solutions exist for most instances. However, current approaches fail to adequately solve a particular class of real-world “difficult” instances which are characterized by a large number of sinks, variations in sink criticalities, and varying polarity requirements. We propose a new Steiner tree construction called C-Tree for these instance types. When combined with van Ginneken style buffer insertion, C-Tree achieves higher quality solutions with fewer resources compared to traditional approaches.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Charles J. Alpert , Anirudh Devgan , Stephen T. Quay, Buffer insertion with accurate gate and interconnect delay computation, Proceedings of the 36th ACM/IEEE conference on Design automation, p.479-484, June 21-25, 1999, New Orleans, Louisiana, United States
[doi> 10.1145/309847.309983]
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C. J. Alpert, T. C. Hu, J. H. Huang, A. B. Kahng, D. Karger, "Prim-Dijkstra Tradeoffs for Improved Performance-Driven Routing Tree Design," IEEE TCAD, 14(7), 1995, 890-896.
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K.D. Boese, A. B. Kahng, B. A. McCoy, G. Robins, "Nearoptimal Critical Sink Routing Tree Constructions", IEEE Trans. on CAD, 14(12), Dec. 1995, pp. 1417-1436.
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Jason Cong , Kwok-Shing Leung , Dian Zhou, Performance-driven interconnect design based on distributed RC delay model, Proceedings of the 30th international conference on Design automation, p.606-611, June 14-18, 1993, Dallas, Texas, United States
[doi> 10.1145/157485.165065]
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T. F. Gonzalez, "Clustering to Minimize the Maximum Intercluster Distance", Theoretical Comp. Sci., 38, 293-306, 1985.
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John Lillis , Chung-Kuan Cheng , Ting-Ting Y. Lin , Ching-Yen Ho, New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing, Proceedings of the 33rd annual conference on Design automation, p.395-400, June 03-07, 1996, Las Vegas, Nevada, United States
[doi> 10.1145/240518.240594]
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J. Lillis, C.-K. Cheng and T.-T. Y. Lin, "Optimal Wire Sizing and Buffer Insertion for Low Power and a Generalized Delay Model", IEEE J. Solid-State Circuits, 31(3), 1996, 437-447.
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L. P. P. P. van Ginneken, "Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay", Intl. Symposium on Circuits and Systems, 1990, pp. 865-868.
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CITED BY 11
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Miloš Hrkić , John Lillis, Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
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Jingyu Xu , Xianlong Hong , Tong Jing , Yici Cai , Jun Gu, An efficient hierarchical timing-driven Steiner tree algorithm for global routing, Integration, the VLSI Journal, v.35 n.2, p.69-84, August 2003
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Sampath Dechu , Zion Cien Shen , Chris C. N. Chu, An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.361-366, January 27-30, 2004, Yokohama, Japan
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Jiang Hu , Charles J. Alpert , Stephen T. Quay , Gopal Gandham, Buffer insertion with adaptive blockage avoidance, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
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Christoph Bartoschek , Stephan Held , Dieter Rautenbach , Jens Vygen, Efficient generation of short and fast repeater tree topologies, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
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