On pipelining dynamic instruction scheduling logic

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On pipelining dynamic instruction scheduling logic

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International Symposium on Microarchitecture archive
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture table of contents

Monterey, California, United States

Pages: 57 - 66

Year of Publication: 2000

ISBN:1-58113-196-8

Authors

Jared Stark	Microprocessor Research Labs, Intel Corporation
Mary D. Brown	Dept. of Electrical and Computer Engineering, The University of Texas at Austin
Yale N. Patt	Dept. of Electrical and Computer Engineering, The University of Texas at Austin

Sponsors

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
IEEE TC - MICRO : IEEE TC - MICRO

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ACM New York, NY, USA

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Downloads (6 Weeks): 5, Downloads (12 Months): 79, Citation Count: 31

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Michael Butler , Yale Patt, An investigation of the performance of various dynamic scheduling techniques, Proceedings of the 25th annual international symposium on Microarchitecture, p.1-9, December 01-04, 1992, Portland, Oregon, United States
	2	IA-32 Intel Architecture Software Developer's Manual With Preliminary Willamette Architecture Information Volume 1: Basic Architecture, Intel Corporation, 2000.
	3	Subbarao Palacharla , Norman P. Jouppi , J. E. Smith, Complexity-effective superscalar processors, Proceedings of the 24th annual international symposium on Computer architecture, p.206-218, June 01-04, 1997, Denver, Colorado, United States
	4	R. M. Tomasulo, An efficient algorithm for exploiting multiple arithmetic units, IBM Journal of Research and Development, vol. 11, pp. 2533, January 1967.
	5	Kenneth C. Yeager, The MIPS R10000 Superscalar Microprocessor, IEEE Micro, v.16 n.2, p.28-40, April 1996 [doi>10.1109/40.491460]
	6	A. Yu, Client Architecture for the New Millennium, Intel Corporation, February 2000. Spring 2000 Intel Developer Forum Keynote Presentation.

CITED BY 31

	Mary D. Brown , Jared Stark , Yale N. Patt, Select-free instruction scheduling logic, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas
	André Seznec , Eric Toullec , Olivier Rochecouste, Register write specialization register read specialization: a path to complexity-effective wide-issue superscalar processors, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
	M. S. Hrishikesh , Doug Burger , Norman P. Jouppi , Stephen W. Keckler , Keith I. Farkas , Premkishore Shivakumar, The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays, ACM SIGARCH Computer Architecture News, v.30 n.2, May 2002
	Dan Ernst , Andrew Hamel , Todd Austin, Cyclone: a broadcast-free dynamic instruction scheduler with selective replay, ACM SIGARCH Computer Architecture News, v.31 n.2, May 2003
	Ilhyun Kim , Mikko H. Lipasti, Half-price architecture, ACM SIGARCH Computer Architecture News, v.31 n.2, May 2003
	Dan Ernst , Todd Austin, Efficient dynamic scheduling through tag elimination, ACM SIGARCH Computer Architecture News, v.30 n.2, May 2002
	Yu Bai , R. Iris Bahar, A low-power in-order/out-of-order issue queue, ACM Transactions on Architecture and Code Optimization (TACO), v.1 n.2, p.152-179, June 2004
	Adrián Cristal , José F. Martínez , Josep Llosa , Mateo Valero, A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors, ACM SIGARCH Computer Architecture News, v.32 n.3, p.3-10, June 2004
	Steven E. Raasch , Nathan L. Binkert , Steven K. Reinhardt, A scalable instruction queue design using dependence chains, ACM SIGARCH Computer Architecture News, v.30 n.2, May 2002
	Joseph J. Sharkey , Dmitry V. Ponomarev , Kanad Ghose , Oguz Ergin, Instruction packing: reducing power and delay of the dynamic scheduling logic, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	R. González , A. Cristal , M. Pericas , M. Valero , A. Veidenbaum, An asymmetric clustered processor based on value content, Proceedings of the 19th annual international conference on Supercomputing, June 20-22, 2005, Cambridge, Massachusetts
	Viji Srinivasan , David Brooks , Michael Gschwind , Pradip Bose , Victor Zyuban , Philip N. Strenski , Philip G. Emma, Optimizing pipelines for power and performance, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
	Edward Brekelbaum , Jeff Rupley , Chris Wilkerson , Bryan Black, Hierarchical Scheduling Windows, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
	Shiliang Hu , James E. Smith, Using Dynamic Binary Translation to Fuse Dependent Instructions, Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization, p.213, March 20-24, 2004, Palo Alto, California
	Peter G. Sassone , D. Scott Wills, Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.7-17, December 04-08, 2004, Portland, Oregon
	Anne Bracy , Prashant Prahlad , Amir Roth, Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.18-29, December 04-08, 2004, Portland, Oregon
	Rajesh Vivekanandham , Bharadwaj Amrutur , R. Govindarajan, A scalable low power issue queue for large instruction window processors, Proceedings of the 20th annual international conference on Supercomputing, June 28-July 01, 2006, Cairns, Queensland, Australia
	Joseph J. Sharkey , Dmitry V. Ponomarev , Kanad Ghose , Oguz Ergin, Instruction packing: Toward fast and energy-efficient instruction scheduling, ACM Transactions on Architecture and Code Optimization (TACO), v.3 n.2, p.156-181, June 2006
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	Hans Vandierendonck , Philippe Manet , Thibault Delavallee , Igor Loiselle , Jean-Didier Legat, By-passing the out-of-order execution pipeline to increase energy-efficiency, Proceedings of the 4th international conference on Computing frontiers, May 07-09, 2007, Ischia, Italy
	Joseph Sharkey , Deniz Balkan , Dmitry Ponomarev, Adaptive reorder buffers for SMT processors, Proceedings of the 15th international conference on Parallel architectures and compilation techniques, September 16-20, 2006, Seattle, Washington, USA
	Peter G. Sassone , Jeff Rupley, II , Edward Brekelbaum , Gabriel H. Loh , Bryan Black, Matrix scheduler reloaded, ACM SIGARCH Computer Architecture News, v.35 n.2, May 2007
	Angshuman Parashar , Sudhanva Gurumurthi , Anand Sivasubramaniam, A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy, ACM SIGARCH Computer Architecture News, v.32 n.2, p.376, March 2004
	Xiaoyao Liang , David Brooks, Mitigating the Impact of Process Variations on Processor Register Files and Execution Units, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, p.504-514, December 09-13, 2006
	T. N. Vijaykumar , Zeshan Chishti, Wire Delay is Not a Problem for SMT (In the Near Future), ACM SIGARCH Computer Architecture News, v.32 n.2, p.40, March 2004
	Emil Talpes , Diana Marculescu, Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines, ACM SIGARCH Computer Architecture News, v.33 n.2, p.310-321, May 2005
	Ilhyun Kim , Mikko H. Lipasti, Macro-op Scheduling: Relaxing Scheduling Loop Constraints, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.277, December 03-05, 2003
	Adrian Cristal , Josep Llosa , Mateo Valero , Daniel Ortega, Future ILP processors, International Journal of High Performance Computing and Networking, v.2 n.1, p.1-10, March 2004
	Francis Tseng , Yale N. Patt, Achieving Out-of-Order Performance with Almost In-Order Complexity, ACM SIGARCH Computer Architecture News, v.36 n.3, p.3-12, June 2008
	Won W. Ro , Jean-Luc Gaudiot, A low-complexity microprocessor design with speculative pre-execution, Journal of Systems Architecture: the EUROMICRO Journal, v.54 n.12, p.1101-1112, December, 2008
	Joseph J. Sharkey , Dmitry V. Ponomarev, Exploiting Operand Availability for Efficient Simultaneous Multithreading, IEEE Transactions on Computers, v.56 n.2, p.208-223, February 2007