A power reduction technique with object code merging for application specific embedded processors

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A power reduction technique with object code merging for application specific embedded processors

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Paris, France

Pages: 617 - 623

Year of Publication: 2000

ISBN:1-58113-244-1

Authors

Tohru Ishihara	Department of Computer Science and Communication Engineering, Graduate School of Information Science and Electrical Engineering, Kyushu University, 6-1 Kasuga-koen, Kasuga-shi, Fukuoka 816-8580, Japan
Hiroto Yasuura	Department of Computer Science and Communication Engineering, Graduate School of Information Science and Electrical Engineering, Kyushu University, 6-1 Kasuga-koen, Kasuga-shi, Fukuoka 816-8580, Japan

Sponsors

EDAA : European Design Automation Association
SIGDA: ACM Special Interest Group on Design Automation
ECSI :
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS : Computer Society
IFIP : International Federation for Information Processing

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 12, Citation Count: 14

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Nikolaos Bellas Ibrahim Hajj , George Stamoulis , N. Bellas , C. Polychronopoulos, Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors, Proceedings of the 1998 international symposium on Low power electronics and design, p.70-75, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280788]
	2	Ching-Long Su , Alvin M. Despain, Cache design trade-offs for power and performance optimization: a case study, Proceedings of the 1995 international symposium on Low power design, p.63-68, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224093]
	3	Yukihiro Yoshida , Bao-Yu Song , Hiroyuki Okuhata , Takao Onoye , Isao Shirakawa, An object code compression approach to embedded processors, Proceedings of the 1997 international symposium on Low power electronics and design, p.265-268, August 18-20, 1997, Monterey, California, United States [doi>10.1145/263272.263349]
	4	K. Ogawa , M. Kohno , F. Kitamura, PASTEL: a parameterized memory characterization system, Proceedings of the conference on Design, automation and test in Europe, p.15-21, February 23-26, 1998, Le Palais des Congrés de Paris, France
	5	H. Shinohara T. Yoshihara H. Takagi S. Nagao S. Kayano M. Yoshimoto, K. Anami and T. Nakano. "A Divided Word-Line Structure in the Staticture in the Static RAM and its Application to a 64K Full CMOS RAM". IEEE Journal of Solid-State Circuits, pages 479-485, June 1983.
	6	M. Isobe, J. Matsunaga, T. Sakurai, T. Ohtani, K. Sawada, H. Nozawa, T. Iszuka and S. Kohyama. "A Low Power 46ns 256K bit CMOS Static RAM with Dynamic Double Word Line". IEEE Journal of Solid State Circuits, SC-19(5):578-585, May 1984.
	7	Edwin de Angel , Earl E. Swartzlander, Jr., Survey of low power techniques for ROMs, Proceedings of the 1997 international symposium on Low power electronics and design, p.7-11, August 18-20, 1997, Monterey, California, United States [doi>10.1145/263272.263274]
	8	T. Sakurai, and T. Iizuka. "Double Word Line and Bit Line Structure for VLSI RAMs-Reduction of Word Line and Bit Line Delay-". In Extended Abstracts of the 15th Conf. on Solid State Devices and Materials, pages 269-272, 1983.
	9	Luca Benini , Alberto Macii , Enrico Macii , Massimo Poncino, Selective instruction compression for memory energy reduction in embedded systems, Proceedings of the 1999 international symposium on Low power electronics and design, p.206-211, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313927]
	10	John L. Hennessy , David A. Patterson, Computer architecture (2nd ed.): a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1996

CITED BY 14

	Tohru Ishihara , Kunihiro Asada, A system level memory power optimization technique using multiple supply and threshold voltages, Proceedings of the 2001 conference on Asia South Pacific design automation, p.456-461, January 2001, Yokohama, Japan
	Rajeshwari Banakar , Stefan Steinke , Bo-Sik Lee , M. Balakrishnan , Peter Marwedel, Scratchpad memory: design alternative for cache on-chip memory in embedded systems, Proceedings of the tenth international symposium on Hardware/software codesign, May 06-08, 2002, Estes Park, Colorado
	Luca Benini , Alberto Macii , Massimo Poncino, Energy-aware design of embedded memories: A survey of technologies, architectures, and optimization techniques, ACM Transactions on Embedded Computing Systems (TECS), v.2 n.1, p.5-32, February 2003
	Yun Cao , Hiroyuki Tomiyama , Takanori Okuma , Hiroto Yasuura, Data memory design considering effective bitwidth for low-energy embedded systems, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan
	Frank Vahid , Ann Gordon-Ross, A self-optimizing embedded microprocessor using a loop table for low power, Proceedings of the 2001 international symposium on Low power electronics and design, p.219-224, August 2001, Huntington Beach, California, United States
	Takanori Okuma , Yun Cao , Masanori Muroyama , Hiroto Yasuura, Reducing access energy of on-chip data memory considering active data bitwidth, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Ann Gordon-Ross , Frank Vahid, Frequent loop detection using efficient non-intrusive on-chip hardware, Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems, October 30-November 01, 2003, San Jose, California, USA
	Stefan Steinke , Nils Grunwald , Lars Wehmeyer , Rajeshwari Banakar , M. Balakrishnan , Peter Marwedel, Reducing energy consumption by dynamic copying of instructions onto onchip memory, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan
	Shlomo Weiss , Roman Tsikel, Approximate prefix coding for system-on-a-chip programs, Journal of Systems Architecture: the EUROMICRO Journal, v.48 n.13-15, p.367-375, May 2003
	Roman Lysecky , Susan Cotterell , Frank Vahid, A fast on-chip profiler memory, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Ann Gordon-Ross , Frank Vahid, Frequent Loop Detection Using Efficient Nonintrusive On-Chip Hardware, IEEE Transactions on Computers, v.54 n.10, p.1203-1215, October 2005
	Murali Jayapala , Francisco Barat , Tom Vander Aa , Francky Catthoor , Henk Corporaal , Geert Deconinck, Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors, IEEE Transactions on Computers, v.54 n.6, p.672-683, June 2005
	Ann Gordon-Ross , Susan Cotterell , Frank Vahid, Tiny instruction caches for low power embedded systems, ACM Transactions on Embedded Computing Systems (TECS), v.2 n.4, p.449-481, November 2003
	Tom Vander Aa , Murali Jayapala , Francisco Barat , Geert Deconinck , Rudy Lauwereins , Henk Corporaal , Francky Catthoor, Instruction buffering exploration for low energy embedded processors, Journal of Embedded Computing, v.1 n.3, p.341-351, August 2005