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E-PROOFS: a CMOS bridging fault simulator

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International Conference on Computer Aided Design archive
Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design table of contents

Santa Clara, California, United States

Pages: 268 - 271

Year of Publication: 1992

ISBN:0-89791-540-2

Authors

Gary S. Greenstein	Sunrise Test Systems, 1095 E. Duane Ave. #207, Sunnyvale, CA
Janak H. Patel	ECE Department, University Of Illinois, Urbana-Champaign, Urbana, Illinois

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 13, Citation Count: 12

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M. Abramovici and P. Menon. "A practical approach to fault simulation and test generation for bridging faults", IEEE Transactions on Computers, pages 658- 663, Sept. 1985.
	2	J. Acken. Deriving Accurate Fault Models. PhD thesis, Stanford University, 1988.
	3	lB. Acuna, J. Devernis, A. Pagones, F. Yang, and R.. Saleh. "Simulation techniques for mixed analog/digital circuits," IEEE Journal of Solid-State Circuits, pages 353-363, Apt 1990.
	4	G. S. Choi , R. K. Iyer, FOCUS: An Experimental Environment for Fault Sensitivity Analysis, IEEE Transactions on Computers, v.41 n.12, p.1515-1526, December 1992 [doi>10.1109/12.214660]
	5	F. Joel Ferguson , Tracy Larrabee, Test Pattern Generation for Realistic Bridge Faults in CMOS ICs, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.492-499, October 26-30, 1991
	6	G. S. Greenstein. CMOS Bridging Fault Simulation. Master's thesis, University of Illinois at Urbana- Champaign, 1992.
	7	Y.-C. Ju, F. Yang, and R. Saleh. "Mixed-mode incremental simulation and concurrent fault simulation," In Proceedings of the IEEE international Conference on Computer-Aided Design, pages 158-161, Nov. 1990.
	8	T. Lee and I. Haij. "A switch-level matrix approach to transistor-levd fault simulation," In Proceedings of the IEEE international Conference on Computer- Aided Design, pages 554-557, Nov. 1991.
	9	T. Niermann. Techniques For Sequential Circuit Automatic Test Generation. PhD thesis, University of Illinois at Urbana-Champaign, 1991.
	10	T. Niermann, W. Cheng, and J. Patel. "PROOFS: A fast, memory-efficient sequential circuit fault simulator," IEEE Transactions on Computer-Aided Design, pages 198-207, Feb. 1992.
	11	R. Rajsuman, Y. Malaiya, and A. Jayasumana. "Limits of switch level analysis for bridging faults," IEEE Transactions on Computer-Aided Design, pages 807- 811, July 1989.
	12	T. Storey and W. Maly. "CMOS bridging fault detection," In Proceedings of the IEEE International Test Conference, pages 1123-1132, Sept. 1990.

CITED BY 12

	Srikanth Venkataraman , W. Kent Fuchs, A deductive technique for diagnosis of bridging faults, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.562-567, November 09-13, 1997, San Jose, California, United States
	Tzuhao Chen , Ibrahim N. Hajj, GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/IDDQ testing environment, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.555-561, November 09-13, 1997, San Jose, California, United States
	Ismed Hartanto , Srikanth Venkataraman , W. Kent Fuchs , Elizabeth M. Rudnick , Janak H. Patel , Sreejit Chakravarty, Diagnostic simulation of stuck-at faults in sequential circuits using compact lists, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.4, p.471-489, October 2001
	Amir Attarha , Mehradad Nourani , Carco Lucas, Modeling and simulation of real defects using fuzzy logic, Proceedings of the 37th conference on Design automation, p.631-636, June 05-09, 2000, Los Angeles, California, United States
	Kuen-Jong Lee , Jing-Jou Tang , Tsung-Chu Huang, BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.2, p.194-218, April 1999
	Zhanping Chen , Liqiong Wei , Kaushik Roy, On effective I_DDQ Testing of low-voltage CMOS circuits using leakage control techniques, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.5, p.718-725, October 2001
	Jonathan Bradford , Hartmut Delong , Ilia Polian , Bernd Becker, Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting, Journal of Electronic Testing: Theory and Applications, v.19 n.4, p.387-395, August 2003
	Karen Panetta Lentz , Jamie Heller , Pier Luca Montessoro, System Verification Using Multilevel Concurrent Simulation, IEEE Micro, v.19 n.1, p.60-67, January 1999
	Brian Chess , Tracy Larrabee, Logic Testing of Bridging Faults in CMOS Integrated Circuits, IEEE Transactions on Computers, v.47 n.3, p.338-345, March 1998
	Piet Engelke , Ilia Polian , Michel Renovell , Bernd Becker, Automatic Test Pattern Generation for Resistive Bridging Faults, Journal of Electronic Testing: Theory and Applications, v.22 n.1, p.61-69, February 2006
	Donald Shaw , Dhamin Al-Khalili , Come Rozon, Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries, Integration, the VLSI Journal, v.39 n.4, p.382-406, July 2006
	Jue Wu , Gary S. Greenstein , Elizabeth M. Rudnick, A fault list reduction approach for efficient bridge fault diagnosis, Proceedings of the conference on Design, automation and test in Europe, p.61-es, January 1999, Munich, Germany