Improving sampling efficiency for system level power estimation

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Improving sampling efficiency for system level power estimation

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1998 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 115 - 117

Year of Publication: 1998

ISBN:1-58113-059-7

Authors

Chih-Shun Ding	Rockwell Semiconductor Systems, Rockwell International Corporation, Newport Beach, CA
Cheng-Ta Hsieh	Department of Electrical Engineering - Systems, University of Southern California Los Angeles, CA
Massoud Pedram	Department of Electrical Engineering - Systems, University of Southern California Los Angeles, CA

Sponsors

IEEE-SSCS : Solid Stat Circuits Council
SIGDA: ACM Special Interest Group on Design Automation
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 1, Downloads (12 Months): 7, Citation Count: 0

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ABSTRACT

In this paper, we propose an efficient statistical sampling technique which is suitable for estimating the total power consumption of a large VLSI system. The basic idea is to generate simulation units for each module in the system independently and then form samples of the system power by randomly selecting simulation units for each module. Hence, sampling is performed both temporally (across different clock cycles) and spatially (across different modules). A module clustering step ensures that the module types are compatible with this sampling strategy. Experimental results show a 4x reduction in the simulation time compared to existing Monte-Carlo simulation techniques.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	R. Butch, F. N. Najm, P. Yang, and T. Trick. A Monte Carlo approach for power estimation. IE~;E Transactions on VLSI Systems, 1(1):63-71, March 1993.
	2	Chih-Shun Ding , Cheng-Ta Hsieh , Qing Wu , Massoud Pedram, Stratified random sampling for power estimation, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.576-582, November 10-14, 1996, San Jose, California, United States
	3	L. Yuan , C. Teng , S. Kang, Statistical estimation of average power dissipation in CMOS VLSI circuits using nonparametric techniques, Proceedings of the 1996 international symposium on Low power electronics and design, p.73-78, August 12-14, 1996, Monterey, California, United States
	4	C.-S. Ding. Probabilistic and Statistical Sampling Techniques for Efficient Power Estimation in VLSI Circuits. In Ph.D Dissertation, USC, May 1998.