Timing driven floorplanning on programmable hierarchical targets

ABSTRACT

The goal of this paper is to perform a timing optimization of a circuit described b y a network of cells on a target structure whose connection delays ha v ediscrete values follo wing its hierarch y. The circuits is modelled by a set of timed cones whose delay histograms allow their classification into critical, potential critical and neutral cones according to predicted delays. The floorplanning is then guided b y this cone structuring and has two innov ativ e features:first, it is shown that the placement of the elements of the neutral cones has no impact on timing results, th us a significant reduction is obtained; second, despite a greedy approach, a near optimal floorplan is achieved in a large number of examples.

REFERENCES

• SawTho95: Prashant Sawkar , Donald Thomas, Multi-way partitioning for minimum delay for look-up table based FPGAs, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.201-210, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217530]
• SauBra93: G. Saucier , D. Brasen , J. P. Hiol, Partitioning with cone structures, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.236-239, November 07-11, 1993, Santa Clara, California, United States
• KatsKoWaYo95: Yoshinori Katsura , Tetsushi Koide , Shin'ichi Wakabayashi , Noriyosh Yoshida, A new system partitioning method under performance and physical constraints for multi-chip modules, Proceedings of the 1995 conference on Asia Pacific design automation (CD-ROM), p.20-es, August 29-September 01, 1995, Makuhari, Massa, Chiba, Japan [doi>10.1145/224818.224887]
• YousSait95: Habib Youssef , Sadiq M. Sait , Khalid J. Al-Farra, Timing influenced force directed floorplanning, Proceedings of the conference on European design automation, p.156-161, September 18-22, 1995, Brighton, England
• SwaSe95: William Swartz , Carl Sechen, Timing driven placement for large standard cell circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.211-215, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217531]
• YanWon95: H. ~ang, D. F. Wong "Circuit clustering for dell' minimization under area and pin constraints", Proc. of iEEE Int. Conf. on Comput.-Aided Design, 1995: 65-70.
• RoySe94: Kalapi Roy-Neogi , Carl Sechen, Multiple FPGA partitioning with performance optimization, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.146-152, February 12-14, 1995, Monterey, California, United States [doi>10.1145/201310.201333]
• SauBra93: G. Saucier , D. Brasen , J. P. Hiol, Partitioning with cone structures, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.236-239, November 07-11, 1993, Santa Clara, California, United States
• RajWong93: Rajmohan Rajaraman , D. F. Wong, Optimal clustering for delay minimization, Proceedings of the 30th international conference on Design automation, p.309-314, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164907]
• ShiKuTsay92: M. Shih , E. S. Kuh , R.-S. Tsay, Performance-driven system partitioning on multi-chip modules, Proceedings of the 29th ACM/IEEE conference on Design automation, p.53-56, June 08-12, 1992, Anaheim, California, United States
• HauNaiYof87: P.S. Hauge, R. Nair, E.J. Yoffa, "Circuit placement for predictable performance:', Proc. of IEEE Int. Conf. on Comput.-Aided Design, 1987: 88-91.
• BurYou85: Michael Burstein , Mary N. Youssef, Timing influenced layout design, Proceedings of the 22nd ACM/IEEE conference on Design automation, p.124-130, June 1985, Las Vegas, Nevada, United States [doi>10.1145/317825.317845]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Placement and routing; Layout
  B.8 Performance and Reliability

General Terms:
Algorithms, Design, Experimentation, Performance