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The ISPD98 circuit benchmark suite
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Source International Symposium on Physical Design archive
Proceedings of the 1998 international symposium on Physical design table of contents
Monterey, California, United States
Pages: 80 - 85  
Year of Publication: 1998
ISBN:1-58113-021-X
Author
Charles J. Alpert  IBM Austin Research Laboratory, Austin TX
Sponsors
IEEE-CS : Computer Society
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 12,   Downloads (12 Months): 50,   Citation Count: 85
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ABSTRACT

From 1985-1993, the MCNC regularly introduced and maintained circuit benchmarks for use by the Design Automation community. However, during the last five years, no new circuits have been introduced that can be used for developing fundamental physical design applications, such as partitioning and placement. The largest circuit in the existing set of benchmark suites has over 100,000 modules, but the second largest has just over 25,000 modules, which is small by today's standards. This paper introduces the ISPD98 benchmark suite which consists of 18 circuits with sizes ranging from 13,000 to 210,000 modules. Experimental results for three existing partitioners are presented so that future researchers in partitioning can more easily evaluate their heuristics.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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F. Brglez, D. Bryan and K. Kozminski, "Combinational Profiles of Sequential Benchmark Circuits", International Conference on Circuits and Systems, 1989, pp. 1929-1934.
 
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J. Cmrbers, H.J. Promel and A. Steger, "Finding Clusters in VT,SI Circuits", IEEE/ACM International Conference on Computer Aided Design, 1990, pp. 520-523.
 
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(3. Karypis, R. Aggarwal, V. Kumar and S. Shekhar, "hMetis, A Hypergraph Partitioning Package, Version 1.0", Manuscript, December 1997.
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Y.-C. Wei and C.-K. Cheng, "Towards Efficient Hierarchical Designs by Ratio Cut Partitioning", IEEE/ACM International Conference on Computer Aided Design, 1989, pp. 298-301.

CITED BY  85