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Partitioning-based standard-cell global placement with an exact objective
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Source International Symposium on Physical Design archive
Proceedings of the 1997 international symposium on Physical design table of contents
Napa Valley, California, United States
Pages: 18 - 25  
Year of Publication: 1997
ISBN:0-89791-927-0
Authors
Dennis J.-H. Huang  UCLA Computer Science Dept., Los Angeles, CA
Andrew B. Kahng  UCLA Computer Science Dept., Los Angeles, CA and Cadence Design Systems, Inc., San Jose, CA
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 40,   Citation Count: 28
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
AHK96
C. J. Alpert, L. W. Hagen, and A. B. Kahng. "A Hybrid Multilevel/Genetic Approach for Circuit Partitioning." In Ptoc. ACM/SIGDA PJ~ydcal Design Workshop, pp. 100-105, 1996.
 
Alp96
 
BCL87
 
Bre76
M. A. Breuer. ':Min-cut Placement." Design Automation and Fault-Tolerant Computing, I(4):343-362, 1976.
 
Bre77
 
DD96a
 
DD96b
S. Dutt and W. Deng. "VLSI Circuit Partitioning by Cluster-Removal Using Iterative Improvement Techniques." In Proc, A CM/SIGDA Physical Design Workshop, pp. 92-99, 1996. Also see corresponding Technical Report, Dept. of Electrical Engineering, U. Minnesota.
 
DJA94
K. Doll, F. M. Johannes, and K. J. Antreich. "Iterative Placement Improvement by Network Flow Methods." IEEE Transactions on Computer- Aided Design, 13:1189-1200, 1994.
 
DJS94
K. Doll, F. M. 3ohannes, and G. Sigl. "Iteratire Placement Improvement by Network Flow Methods," IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, 13(10):1189-1199, 1994.
 
DK85
A.E. Dunlop and B. W. Kernighan. "A Procedure for Placement of Standard Cell VLSI Circuits." IEEE Transactions on Computer-Aided Design, 4(1):92-98, 1985.
 
FM82
 
HHK95
 
KL70
B.W. Kernighan and S. Lin. "An Efficient Heuristic Procedure for Partitioning Graphs." Bell Syst, Tech. J., 49(2):291-307, 1970.
 
KSJ91
J. M. Kleinhans, G. Sigl, F. M. Johannes, and K. J. Antreich. "GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization." IEEE Transactions on Computer-Aided Design, 10(3):356-365, 1991.
 
Lau79
 
Len90
 
RE95
B.M. Riess and G. G. Ettelt. ``SPEED: Fast and Efficient Timing Driven Placement." In Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 377-380, 1995.
 
San89
 
San93
SDJ91
 
SK87a
P.R. Suaris and G. Kedem. "Quadrisection: A New Approach to Standard Cell Layout." in Pracee&'ngs of the IEEE/AUM International Conference on Computer-Aided Design, pp. 474-477, 1987.
 
SK87b
P.R. Suaris and G. Kedem. "Standard Cell Placement by Quadrisection." In Proceedings IEEE Intl. Conf. Computer Design, pp. 612-615, 1987.
 
SK88
P.R. Suaris and G. Kedem. "An Algorithm for Quadrisection and Its Application to Standard Cell Placement." IEEE Transactions on Circuits and Systems, 35(3}:294-303, 1988.
 
SK89
P.R. Suaris and G. Kedem. "A Quadrisectionbased Combined Place and Route Scheme for Standard Cells." IEEE Transactions on Computer-Aided Design, 8(3):234-244. 1989.
SM91
 
SS93
SS95
 
Ste97
G. Stenz. 1997. Personal communication.
 
Swa96
W. Swartz, 1996. Personal communication.
 
TK91
R.-S. Tsay and E. S. Kuh. "A Unified Approach to Partitioning and Placement." IEEE Transactions on Circuits and Systems, 38(5):521-533, 1991.
 
TKH88

CITED BY  28

Collaborative Colleagues:
Dennis J.-H. Huang: colleagues
Andrew B. Kahng: colleagues