| Storage assignment to decrease code size |
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ACM SIGPLAN Notices
archive
Volume 30 , Issue 6 (June 1995)
table of contents
Pages: 186 - 195
Year of Publication: 1995
ISSN:0362-1340
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Authors
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Stan Liao
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MIT Department of EECS, Cambridge, MA
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Srinivas Devadas
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MIT Department of EECS, Cambridge, MA
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Kurt Keutzer
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Synopsys, Inc., Mountain View, CA
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Steve Tjiang
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Synopsys, Inc., Mountain View, CA
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Albert Wang
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Synopsys, Inc., Mountain View, CA
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Downloads (6 Weeks): 1, Downloads (12 Months): 11, Citation Count: 35
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ABSTRACT
DSP architectures typically provide indirect addressing modes with auto-increment and decrement. In addition, indexing mode is not available, and there are usually few, if any, general-purpose registers. Hence, it is necessary to use address registers and perform address arithmetic to access automatic variables. Subsuming the address arithmetic into auto-increment and auto-decrement modes improves the size of the generated code.In this paper we present a formulation of the problem of optimal storage assignment such that explicit instructions for address arithmetic are minimized. We prove that for the case of a single address register the decision problem is NP-complete. We then generalize the problem to multiple address registers. For both cases heuristic algorithms are given. Our experimental results indicate an improvement of 3.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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G. Araujo, S. Devadas, K. Keutzer, S. Liao, S. Malik, A. Sudarsanam, S. Tjiang, and A. Wang. Challenges in code generation for embedded processors. In P. Marwedel and G. Goossens, editors, Code Generation for Embedded Processors. Kluwer Academic Publishers, 1995. In press.
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G. Goossens, J. Rabaey, F. Catthoor, J Vanhoof, R. Jain, H. De Man, and J. Vandewalle. A Computer- Aided Design Methodology for Mapping DSP Algorithms onto Custom Multiprocessor Architectures. In Proceedings of IEEE International Symposium on Circuits and Systems, pages 924-925, May 1986.
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Stan Liao , Srinivas Devadas , Kurt Keutzer , Steve Tjiang , Albert Wang, Code optimization techniques for embedded DSP microprocessors, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.599-604, June 12-16, 1995, San Francisco, California, United States
[doi> 10.1145/217474.217596]
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C. Liem, T. May, and P. Paulin. Instruction-Set Matching and Selection for DSP and ASIP Code Generation. In Proceedings of European Design and Test Conference, March 1994.
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Robert Wilson , Robert French , Christopher Wilson , Saman Amarasinghe , Jennifer Anderson , Steve Tjiang , Shih Liao , Chau Tseng , Mary Hall , Monica Lam , John Hennessy, The SUIF Compiler System: a Parallelizing and Optimizing Research Compiler, Stanford University, Stanford, CA, 1994
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CITED BY 35
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Stan Liao , Srinivas Devadas , Kurt Keutzer , Steve Tjiang , Albert Wang, Code optimization techniques for embedded DSP microprocessors, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.599-604, June 12-16, 1995, San Francisco, California, United States
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Mahesh Mehendale , G. Venkatesh , S. D. Sherlekar, Optimized code generation of multiplication-free linear transforms, Proceedings of the 33rd annual conference on Design automation, p.41-46, June 03-07, 1996, Las Vegas, Nevada, United States
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Kumar N. Lalgudi , Marios C. Papaefthymiou , Miodrag Potkonjak, Optimizing systems for effective block-processing: the k-delay problem, Proceedings of the 33rd annual conference on Design automation, p.714-719, June 03-07, 1996, Las Vegas, Nevada, United States
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Markus Lorenz , David Koffmann , Steven Bashford , Rainer Leupers , Peter Marwedel, Optimized address assignment for DSPs with SIMD memory accesses, Proceedings of the 2001 conference on Asia South Pacific design automation, p.415-420, January 2001, Yokohama, Japan
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Gert Goossens , Johan Van Praet , Dirk Lanneer , Werner Geurts , Augusli Kifli , Clifford Liem , Pierre G. Paulin, Embedded software in real-time signal processing systems: design technologies, Readings in hardware/software co-design, Kluwer Academic Publishers, Norwell, MA, 2001
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A. Basu , R. Leupers , P. Marwedel, Register-constrained address computation in DSP programs, Proceedings of the conference on Design, automation and test in Europe, p.929-930, February 23-26, 1998, Le Palais des Congrés de Paris, France
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