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Storage assignment to decrease code size
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Source ACM SIGPLAN Notices archive
Volume 30 ,  Issue 6  (June 1995) table of contents
Pages: 186 - 195  
Year of Publication: 1995
ISSN:0362-1340
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Authors
Stan Liao  MIT Department of EECS, Cambridge, MA
Srinivas Devadas  MIT Department of EECS, Cambridge, MA
Kurt Keutzer  Synopsys, Inc., Mountain View, CA
Steve Tjiang  Synopsys, Inc., Mountain View, CA
Albert Wang  Synopsys, Inc., Mountain View, CA
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 1,   Downloads (12 Months): 11,   Citation Count: 35
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ABSTRACT

DSP architectures typically provide indirect addressing modes with auto-increment and decrement. In addition, indexing mode is not available, and there are usually few, if any, general-purpose registers. Hence, it is necessary to use address registers and perform address arithmetic to access automatic variables. Subsuming the address arithmetic into auto-increment and auto-decrement modes improves the size of the generated code.In this paper we present a formulation of the problem of optimal storage assignment such that explicit instructions for address arithmetic are minimized. We prove that for the case of a single address register the decision problem is NP-complete. We then generalize the problem to multiple address registers. For both cases heuristic algorithms are given. Our experimental results indicate an improvement of 3.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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G. Araujo, S. Devadas, K. Keutzer, S. Liao, S. Malik, A. Sudarsanam, S. Tjiang, and A. Wang. Challenges in code generation for embedded processors. In P. Marwedel and G. Goossens, editors, Code Generation for Embedded Processors. Kluwer Academic Publishers, 1995. In press.
 
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J. A. Fisher. Trace Scheduling: A Technique for Global Microcode Compaction. IEEE Trnsactions on Computers, C-30(7):478-490, 1981.
 
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G. Goossens, J. Rabaey, F. Catthoor, J Vanhoof, R. Jain, H. De Man, and J. Vandewalle. A Computer- Aided Design Methodology for Mapping DSP Algorithms onto Custom Multiprocessor Architectures. In Proceedings of IEEE International Symposium on Circuits and Systems, pages 924-925, May 1986.
 
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C. Liem, T. May, and P. Paulin. Instruction-Set Matching and Selection for DSP and ASIP Code Generation. In Proceedings of European Design and Test Conference, March 1994.
 
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CITED BY  35

Collaborative Colleagues:
Stan Liao: colleagues
Srinivas Devadas: colleagues
Kurt Keutzer: colleagues
Steve Tjiang: colleagues
Albert Wang: colleagues