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Modelling and verification of superscalar Micro-architectures functional approach
Source Recent Advances In Computer Engineering archive
Proceedings of the 12th WSEAS international conference on Computers table of contents
Heraklion, Greece
Pages 446-451  
Year of Publication: 2008
ISBN ~ ISSN:1790-5109 , 978-960-6766-85-5
Authors
S. Merniz  LIRE Laboratory, Computer Science Department, Mentouri University, Constantine, Algeria
M. Benmohammed  LIRE Laboratory, Computer Science Department, Mentouri University, Constantine, Algeria
Publisher
Bibliometrics
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ABSTRACT

Most proof approaches verified a pipelined Micro-Architectural (MA) implementation against an Instruction-Set-Architecture (ISA) specification, and consequently, it was impossible to find a meaningful point where the implementation state and the specification state can be compared easily. An alternative solution to such problem is to verify a pipelined micro-architectural implementation against a sequential multi-cycle implementation. Because both models are formalised in terms of clock cycles, all synchronous intermediate states represent interesting points where the comparison could be achieved easily. Furthermore, by decomposing the state, the overall proof decomposes systematically into a set of verification conditions more simple to reason about and to verify. A major advantage of this elegant choice is the ability to carry out the proof by induction within the same specification language rather than by symbolic simulation through a proof tool which remains very tedious. Also, because both models relate to the MA level, there is no need for a data abstraction function, only a time abstraction function is needed to map between the times used by the two models. The potential features of the proposed proof methodology are demonstrated over the pipelined and the superscalar pipelined MIPS processors within Haskell framework.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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A.C.J. Fox. An algebraic framework for verifying the correctness of hardware with input and output: A formalization in HOL, CALCO 2005, LNCS, 3629, 2005.
 
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A.C.J Fox. Verifying the ARM Block Data Transfer Instructions, DCC 2004, Barcelona, 2004.
 
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S L. Peyton Jones et al, Haskell 98: A non strict, purely functional language. Revised; February 1999. Available at: http://www.haskell.org/onlinereport
 
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S. Merniz, M. Benmohammed, A Methodology for the Formal Verification of RISC Microprocessors A Functional Approach, AICCSA'07, Amman, Jordan, May 2007.
 
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R.E. Bryant, S.K. Lahiri,, S.A. Seshia. Convergence testing in term level bounded model checking. CHARME 2003.

Collaborative Colleagues:
S. Merniz: colleagues
M. Benmohammed: colleagues