Take a look at the new version of this page: [ beta version ]. Tell us what you think.

ABSTRACT

Power dissipation has become a critical design metric in microprocessor-based system design. In a multi-core system, running multiple applications, power and performance can be dynamically traded off using an integrated power management (PM) unit. This PM unit monitors the performance and power of each core and dynamically adjusts the individual voltages and frequencies in order to maximize system performance under a given power budget (usually set by the operating system). This paper presents a performance and power analysis methodology, featuring a simulation model for multi-core systems that can be easily reconfigured for different scenarios and a PM infrastructure for the exploration and analysis of PM algorithms. Two algorithms have been implemented: one for discrete and one for continuous power modes based on non-linear programming. Extensive experiments are reported, illustrating the effect of power management both at the core and the chip level.

REFERENCES

• 1: Luiz André Barroso, The price of performance, Queue, v.3 n.7, September 2005 [doi>10.1145/1095408.1095420]
• 2: G. A. Paleologo , L. Benini , A. Bogliolo , G. De Micheli, Policy optimization for dynamic power management, Proceedings of the 35th annual conference on Design automation, p.182-187, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277094]
• 3: Ed Grochowski , Ronny Ronen , John Shen , Hong Wang, Best of Both Latency and Throughput, Proceedings of the IEEE International Conference on Computer Design, p.236-243, October 11-13, 2004
• 4: Seongmoo Heo , Kenneth Barr , Krste Asanović, Reducing power density through activity migration, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871561]
• 5: Mohamed Gomaa , Michael D. Powell , T. N. Vijaykumar, Heat-and-run: leveraging SMT and CMP to manage power density through the operating system, Proceedings of the 11th international conference on Architectural support for programming languages and operating systems, October 07-13, 2004, Boston, MA, USA
• 6: E. Kursun, C. Y. Cher, A. Buyuktosunoglu, and P. Bose, "Investigating the effects of task scheduling on thermal behavior". 3^rd Workshop on Temperature-Aware Computer Systems (TACS'06), Boston, June 18, 2006.
• 7: K. Nowka, G. Carpenter, E. MacDonald, H. C. Ngo, B. Brock, K. Ishii, T. Nguyen, and J. Burns, "A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling". IEEE Journal of Solid-State Circuits, vol. 37, no. 11, pp. 1600--1608, November 2002.
• 8: G. Magklis, G. Semeraro, D. H. Albonesi, S. G. Dropsho, S. Dwarkadas, and M. L. Scott, "Dynamic frequency and voltage scaling for a multiple-clock-domain microprocessor". IEEE Micro, vol. 23, no. 6, pp. 62--68, Nov/Dec 2003.
• 9: R. McGowen, C. Poirier, C. Bostak, J. Ignowski, M. Millican, W. Parks, and S. Naffziger, "Power and temperature control on a 90-nm Itanium family processor". IEEE Journal of Solid-State Circuits, vol. 41, no. 1, pp. 229--237, January 2006.
• 10: Canturk Isci , Alper Buyuktosunoglu , Chen-Yong Cher , Pradip Bose , Margaret Martonosi, An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, p.347-358, December 09-13, 2006 [doi>10.1109/MICRO.2006.8]
• 11: Srilatha Manne , Artur Klauser , Dirk Grunwald, Pipeline gating: speculation control for energy reduction, Proceedings of the 25th annual international symposium on Computer architecture, p.132-141, June 27-July 02, 1998, Barcelona, Spain
• 12: D. Brooks , P. Bose , V. Srinivasan , M. K. Gschwind , P. G. Emma , M. G. Rosenfield, New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors, IBM Journal of Research and Development, v.47 n.5-6, p.653-670, September 2003
• 13: S. J. Wilton, and N. P. Jouppi, "CACTI: an enhanced cache access and cycle time model". IEEE Journal of Solid-State Circuits, vol. 31, no. 5, pp. 677--688, May 1996.
• 14: Nir Magen , Avinoam Kolodny , Uri Weiser , Nachum Shamir, Interconnect-power dissipation in a microprocessor, Proceedings of the 2004 international workshop on System level interconnect prediction, February 14-15, 2004, Paris, France [doi>10.1145/966747.966750]
• 15: Todd Austin , Eric Larson , Dan Ernst, SimpleScalar: An Infrastructure for Computer System Modeling, Computer, v.35 n.2, p.59-67, February 2002 [doi>10.1109/2.982917]
• 16: David Brooks , Vivek Tiwari , Margaret Martonosi, Wattch: a framework for architectural-level power analysis and optimizations, Proceedings of the 27th annual international symposium on Computer architecture, p.83-94, June 2000, Vancouver, British Columbia, Canada
• 17: A. Bogliolo, L. Benini, E. Lattanzi, and G. De Micheli, "Specification and analysis of power-managed systems". Proceedings of the IEEE, vol. 92, no. 8, pp. 1308--1346, August 2004.
• 18: Reinaldo Bergamaschi , Indira Nair , Gero Dittmann , Hiren Patel , Geert Janssen , Nagu Dhanwada , Alper Buyuktosunoglu , Emrah Acar , Gi-Joon Nam , Dorothy Kucar , Pradip Bose , John Darringer , Guoling Han, Performance modeling for early analysis of multi-core systems, Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis, September 30-October 03, 2007, Salzburg, Austria [doi>10.1145/1289816.1289868]
• 19: J. Tendler, J. S. Dodson, J. S. Fields Jr., H. Le, B. Sinharoy, "POWER4 system microarchitecture". IBM Journal of Research & Development, vol. 46, no. 1, pp. 5--26, January 2002.
• 20: SPEC Standard Performance Evaluation Corporation, www.spec.org.
• 21: S. R. Kunkel, R. J. Eickemeyer, M. H. Lipasti, T. J. Mullins, B. O'Krafka, H. Rosenberg, S. P. VanderWiel, P. L. Vitale, and L. D. Whitley, "A performance methodology for commercial servers". IBM Journal of Research & Development, Vol.44, No.6, November, 2000.
• 22: "OPT++: an object-oriented nonlinear optimization library", http://csmr.ca.sandia.gov/opt++/

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.4 Parallel Architectures

Additional Classification:
  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS
  C.5 COMPUTER SYSTEM IMPLEMENTATION
      C.5.0 General

General Terms:
Design, Experimentation, Measurement, Performance