Area and delay trade-offs in the circuit and architecture design of FPGAs

ABSTRACT

Field-programmable gate arrays (FPGAs) are used in a wide range of markets that have differing cost, performance and power consumption requirements. It would be advantageous if a single device family could serve these varied needs but the economics of catering to this wide distribution of market demands suggest more than one family is appropriate. Consequently, FPGA vendors have moved to provide a more diverse set of families that sit at different points in the area-speed-power design space.

In this work, our goal is to understand the circuit and architectural design attributes of an FPGA that enable trade-offs between area and speed, and to determine the magnitude of the possible trade-offs. This will be useful for architects seeking to determine the number of device families in a suite of offerings, as well as the changes to make between families.

We have found that varying both architecture and transistor sizing of an FPGA allows the effective area to change by a factor of 3.6 from largest to smallest and the speed to change by a factor of 2.6 from fastest to slowest. It is interesting to observe that the range of area and delay trade-offs possible by varying only the transistor sizing of a single architecture is larger than the ranges observed in past architectural experiments. In addition to transistor size, we note that LUT size is one of the most useful parameters for trading off area and delay

REFERENCES

• 1: E. Ahmed and J. Rose. The effect of LUT and cluster size on deep-submicron FPGA performance and density. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(3):288--298, March 2004.
• 2: Altera Corporation. Stratix III device handbook, Nov 2006. ver 1.0.
• 3: Altera Corporation. Cyclone III device handbook, Sept 2007. ver. CIII5V1-1.2.
• 4: T. Bauer. Xilinx. Private Communication.
• 5: Vaughn Betz , Jonathan Rose, VPR: A new packing, placement and routing tool for FPGA research, Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, p.213-222, September 01-03, 1997
• 6: V. Betz and J. Rose. Circuit design, transistor sizing and wire layout of FPGA interconnect. In Proceedings of the 1999 IEEE Custom Integrated Circuits Conference, pages 171--174, 1999.
• 7: Vaughn Betz , Jonathan Rose , Alexander Marquardt, Architecture and CAD for Deep-Submicron FPGAs, Kluwer Academic Publishers, Norwell, MA, 1999
• 8: Lerong Cheng , Phoebe Wong , Fei Li , Yan Lin , Lei He, Device and architecture co-optimization for FPGA power reduction, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, Anaheim, California, USA [doi>10.1145/1065579.1065819]
• 9: Katherine Compton , Akshay Sharma , Shawn Phillips , Scott Hauck, Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems, Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications, p.59-68, September 02-04, 2002
• 10: Jason Cong , John Peck , Yuzheng Ding, RASP: a general logic synthesis system for SRAM-based FPGAs, Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays, p.137-143, February 11-13, 1996, Monterey, California, United States [doi>10.1145/228370.228390]
• 11: A. R. Conn , I. M. Elfadel , W. W. Molzen, Jr. , P. R. O'Brien , P. N. Strenski , C. Visweswariah , C. B. Whan, Gradient-based optimization of custom circuits using a static-timing formulation, Proceedings of the 36th ACM/IEEE conference on Design automation, p.452-459, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309979]
• 12: J.P. Fishburn and A. Dunlop. TILOS: A posynomial programming approach to transistor sizing. In International Conference on Computer Aided Design, pages 326--328, November 1985.
• 13: Michael Hutton , Vinson Chan , Peter Kazarian , Victor Maruri , Tony Ngai , Jim Park , Rakesh Patel , Bruce Pedersen , Jay Schleicher , Sergey Shumarayev, Interconnect enhancements for a high-speed PLD architecture, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, February 24-26, 2002, Monterey, California, USA [doi>10.1145/503048.503050]
• 14: I. Kuon and J. Rose. Measuring the gap between FPGAs and ASICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(2), 2007.
• 15: Lattice Semiconductor Corporation. LatticeECP2/M Family Handbook, Version 01.6, August 2007. http://www.latticesemi.com/dynamic/view_document.cfm?document_id=19028.
• 16: Lattice Semiconductor Corporation. LatticeECP2/M Family Handbook, Version 02.9, July 2007. http://www.latticesemi.com/dynamic/view_document.cfm?document_id=21733.
• 17: E. Lee, G. Lemieux, and S. Mirabbasi. Interconnect driver design for long wires in field-programmable gate arrays. In IEEE International Conference on Field Programmable Technology, pages 89--96, December 2006.
• 18: G. Lemieux, E. Lee, M. Tom, and A. Yu. Directional and single-driver wires in FPGA interconnect. In IEEE International Conference on Field-Programmable Technology, pages 41--48, December 2004.
• 19: David Lewis , Elias Ahmed , Gregg Baeckler , Vaughn Betz , Mark Bourgeault , David Cashman , David Galloway , Mike Hutton , Chris Lane , Andy Lee , Paul Leventis , Sandy Marquardt , Cameron McClintock , Ketan Padalia , Bruce Pedersen , Giles Powell , Boris Ratchev , Srinivas Reddy , Jay Schleicher , Kevin Stevens , Richard Yuan , Richard Cliff , Jonathan Rose, The Stratix II logic and routing architecture, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, February 20-22, 2005, Monterey, California, USA [doi>10.1145/1046192.1046195]
• 20: David Lewis , Vaughn Betz , David Jefferson , Andy Lee , Chris Lane , Paul Leventis , Sandy Marquardt , Cameron McClintock , Bruce Pedersen , Giles Powell , Srinivas Reddy , Chris Wysocki , Richard Cliff , Jonathan Rose, The stratixπ routing and logic architecture, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA [doi>10.1145/611817.611821]
• 21: F. Li, Y. Lin, L. He, D. Chen, and J. Cong. Power modeling and characteristics of field programmable gate arrays. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(11):1712--1724, Nov. 2005.
• 22: Alexander (Sandy) Marquardt , Vaughn Betz , Jonathan Rose, Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.37-46, February 21-23, 1999, Monterey, California, United States [doi>10.1145/296399.296426]
• 23: John K. Ousterhout, Switch-level delay models for digital MOS VLSI, Proceedings of the 21st conference on Design automation, p.542-548, June 25-27, 1984, Albuquerque, New Mexico, United States
• 24: Jan M. Rabaey, Digital integrated circuits: a design perspective, Prentice-Hall, Inc., Upper Saddle River, NJ, 1996
• 25: J. Rubinstein, P. Penfield, and M.A. Horowitz. Signal delay in RC tree networks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2(3):202--211, July 1983.
• 26: S.S. Sapatnekar, V.B. Rao, P. Vaidya, and K. Sung-Mo. An exact solution to the transistor sizing problem for CMOS circuits using convex optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 12(11):1621--1634, November 1993.
• 27: STMicroelectronics. 90nm CMOS090 Design Platform, 2005. http://www.st.com/stonline/products/technologies/soc/90plat.htm.
• 28: Ivan Sutherland , Bob Sproull , David Harris, Logical effort: designing fast CMOS circuits, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1999
• 29: Synopsys. HSPICE. http://www.synopsys.com/products/mixedsignal/hspice/hspice.html.
• 30: Synopsys. NanoSim. http://www.synopsys.com/products/mixedsignal/nanosim/nanosim.html.
• 31: Xilinx. Spartan-3e, November 2006. Ver. 3.4.
• 32: Xilinx. Virtex-5 user guide, October 2006. UG190 (v2.1).
• 33: S. Yang. Logic synthesis and optimization benchmarks user guide version 3.0. Technical report, Microelectronics Center of North Carolina, Jan 1991.
• 34: S.P. Young, T.J. Bauer, K. Chaudhary, and S. Krishnamurthy. FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines, Aug 1999. US Patent 5,942,913.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles

General Terms:
Design, Measurement, Performance

Keywords:
FPGA, architecture, optimization