Efficient and scalable compiler-directed energy optimization for realtime applications

ABSTRACT

With continuing shrinkage of technology feature sizes, the share of leakage in total energy consumption of digital systems continues to grow. Coordinated supply voltage and body bias throttling enables the compiler to better optimize the total energy consumption of the system in future technology nodes. We present a compilation technique that targets realtime applications running on embedded processors with combined dynamic voltage scaling (DVS) and adaptive body biasing (ABB) capabilities. Considering the delay and energy penalty of switching between operating modes of the processor, our compiler judiciously inserts mode-switch instructions in selected locations of the code and generates executable binary that is guaranteed to meet the deadline constraint. More importantly, our algorithm runs very fast and comes reasonably close to the theoretical limit of energy optimization using DVS+ABB. At 65nm technology, we improve the energy dissipation of the generated code by an average of 33.20% under deadline constraints. While our technique's improvement in energy dissipation over conventional DVS is marginal (6.91%) at 130nm, the average improvement continues to grow to 13.19%, 22.97%, and 33.21% for 90nm, 65nm, and 45nm technology nodes, respectively. Compared to a recent ILP-based competitor, we improve the runtime by more than three orders of magnitude, while producing improved results.

REFERENCES

• 1: Nevine AbouGhazaleh , Daniel Mossé , Bruce Childers , Rami Melhem , Matthew Craven, Collaborative Operating System and Compiler Power Management for Real-Time Applications, Proceedings of the The 9th IEEE Real-Time and Embedded Technology and Applications Symposium, p.133, May 27-30, 2003
• 2: Alexandru Andrei , Marcus Schmitz , Petru Eles , Zebo Peng , Bashir M. Al-Hashimi, Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems, Proceedings of the conference on Design, automation and test in Europe, p.10518, February 16-20, 2004
• 3: A. Azevedo , I. Issenin , R. Cornea , R. Gupta , N. Dutt , A. Veidenbaum , A. Nicolau, Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints, Proceedings of the conference on Design, automation and test in Europe, p.168, March 04-08, 2002
• 4: Berkeley-model. http://www-device.eecs.berkeley.edu/~ptm/introduction.html.
• 5: Burd, T., Pering, T., Stratakos, A., and Brodersen, R. 2000. A dynamic voltage scaled microprocessor system. IEEE J. Solid-State Circ. 35, 11 (Nov.), 1571--1580.
• 6: David Duarte , Yuh-Fang Tsai , Narayanan Vijaykrishnan , Mary Jane Irwin, Evaluating Run-Time Techniques for Leakage Power Reduction, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.31, January 07-11, 2002
• 7: H-S Kim, Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes, Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02), p.382, September 16-18, 2002
• 8: M. R. Guthaus , J. S. Ringenberg , D. Ernst , T. M. Austin , T. Mudge , R. B. Brown, MiBench: A free, commercially representative embedded benchmark suite, Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop, p.3-14, December 02-02, 2001 [doi>10.1109/WWC.2001.15]
• 9: Chung-Hsing Hsu , Ulrich Kremer, The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction, Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation, June 09-11, 2003, San Diego, California, USA
• 10: Po-Kuan Huang , Soheil Ghiasi, Leakage-aware intraprogram voltage scaling for embedded processors, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA [doi>10.1145/1146909.1147003]
• 11: Kao, J., Miyazaki, M., and Chandrakasan, A. 2002. A 175-mv multiply-accumulate unit using an adaptive supply voltage and body bias architecture. J. Solid-State Circu. 37, 11 (Nov.), 1545--1554.
• 12: Ali Keshavarzi , Siva Narendra , Shekhar Borkar , Charles Hawkins , Kaushik Roy , Vivek De, Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's, Proceedings of the 1999 international symposium on Low power electronics and design, p.252-254, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313937]
• 13: Woonseok Kim , Jihong Kim , Sang Lyul Min, Dynamic voltage scaling algorithm for fixed-priority real-time systems using work-demand analysis, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871605]
• 14: Yau-Tsun Steven Li , Sharad Malik , Andrew Wolfe, Performance estimation of embedded software with instruction cache modeling, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.3, p.257-279, July 1999 [doi>10.1145/315773.315778]
• 15: Longrun. 2007. http://www.transmeta.com/technology/architecture/longrun.html.
• 16: Steven M. Martin , Krisztian Flautner , Trevor Mudge , David Blaauw, Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.721-725, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774678]
• 17: Padmanabhan Pillai , Kang G. Shin, Real-time dynamic voltage scaling for low-power embedded operating systems, Proceedings of the eighteenth ACM symposium on Operating systems principles, October 21-24, 2001, Banff, Alberta, Canada
• 18: Gang Qu, What is the limit of energy saving by dynamic voltage scaling?, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
• 19: Siddharth Rele , Santosh Pande , Soner Önder , Rajiv Gupta, Optimizing Static Power Dissipation by Functional Units in Superscalar Processors, Proceedings of the 11th International Conference on Compiler Construction, p.261-275, April 08-12, 2002
• 20: Smith, M. and Holloway, G. 2002. An introduction to machine suif and its portable libraries for analysis and optimization. Tech. Rep., Division of Engineering and Applied Sciences, Harvard University.
• 21: Vivy Suhendra , Tulika Mitra , Abhik Roychoudhury , Ting Chen, Efficient detection and exploitation of infeasible paths for software timing analysis, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA [doi>10.1145/1146909.1147002]
• 22: Fen Xie , Margaret Martonosi , Sharad Malik, Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modeling, ACM Transactions on Architecture and Code Optimization (TACO), v.1 n.3, p.323-367, September 2004 [doi>10.1145/1022969.1022973]
• 23: Xscale. 2007. http://www.intel.com/design/intelxscale.
• 24: Le Yan , Jiong Luo , Niraj K. Jha, Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.30, November 09-13, 2003 [doi>10.1109/ICCAD.2003.50]
• 25: F. Yao , A. Demers , S. Shenker, A scheduling model for reduced CPU energy, Proceedings of the 36th Annual Symposium on Foundations of Computer Science (FOCS'95), p.374, October 23-25, 1995
• 26: Yi-Ping You , Chingren Lee , Jenq Kuen Lee, Compilers for leakage power reduction, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.1, p.147-164, January 2006 [doi>10.1145/1124713.1124723]
• 27: W. Zhang , M. Kandemir , N. Vijaykrishnan , M. J. Irwin , V. De, Compiler Support for Reducing Leakage Energy Consumption, Proceedings of the conference on Design, Automation and Test in Europe, p.11146, March 03-07, 2003

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Real-time and embedded systems

Additional Classification:
  D. Software
  D.3 PROGRAMMING LANGUAGES
      D.3.4 Processors
          Subjects: Compilers

General Terms:
Algorithms, Performance

Keywords:
Leakage, energy-aware compiler, technology scaling