| Reconfigurable hybrid interconnection for static and dynamic scientific applications |
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Conference On Computing Frontiers
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Proceedings of the 4th international conference on Computing frontiers
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Ischia, Italy
SESSION: Reconfigurable architectures
table of contents
Pages: 183 - 194
Year of Publication: 2007
ISBN:978-1-59593-683-7
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Authors
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Shoaib Kamil
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Lawrence Berkeley National Lab / CS Dept. UC Berkeley, Berkeley, CA
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Ali Pinar
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Lawrence Berkeley National Lab, Berkeley, CA
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Daniel Gunter
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Lawrence Berkeley National Lab, Berkeley, CA
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Michael Lijewski
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Lawrence Berkeley National Lab, Berkeley, CA
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Leonid Oliker
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Lawrence Berkeley National Lab, Berkeley, CA
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John Shalf
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Lawrence Berkeley National Lab, Berkeley, CA
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ABSTRACT
As we enter the era of peta-scale computing, system architects must plan for machines composed of tens or even hundreds of thousands of processors. Although fully connected networks such as fat-tree configurations currently dominate HPC interconnect designs, such approaches are inadequate for ultra-scale concurrencies due to the superlinear growth of component costs. Traditional low-degree interconnect topologies, such as 3D tori, have reemerged as a competitive solution due to the linear scaling of system components relative to the node count; however, such networks are poorly suited for the requirements of many scientific applications at extreme concurrencies. To address these limitations, we propose HFAST, a hybrid switch architecture that uses circuit switches to dynamically reconfigure lower-degree interconnects to suit the topological requirements of a given scientific application. This work presents several new research contributions. We develop an optimization strategy for HFAST mappings and demonstrate that efficiency gains can be attained across a broad range of static numerical computations. Additionally, we conduct an extensive analysis of the communication characteristics of a dynamically adapting mesh calculation and show that the HFAST approach can achieve significant advantages, even when compared with traditional fat-tree configurations. Overall results point to the promising potential of utilizing hybrid reconfigurable networks to interconnect future peta-scale architectures, for both static and dynamically adapting applications.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY
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Gilbert Hendry , Shoaib Kamil , Aleksandr Biberman , Johnnie Chan , Benjamin G. Lee , Marghoob Mohiyuddin , Ankit Jain , Keren Bergman , Luca P. Carloni , John Kubiatowicz , Leonid Oliker , John Shalf, Analysis of photonic networks for a chip multiprocessor using scientific applications, Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, p.104-113, May 10-13, 2009
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