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Reducing cache misses by application-specific re-configurable indexing
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Source International Conference on Computer Aided Design archive
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design table of contents
Pages: 125 - 130  
Year of Publication: 2004
ISBN:0-7803-8702-3
Authors
K. Patel  Politecnico di Torino, Italy
E. Macii  Politecnico di Torino, Italy
L. Benini  Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M. Poncino  Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
Publisher
IEEE Computer Society  Washington, DC, USA
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Downloads (6 Weeks): 3,   Downloads (12 Months): 16,   Citation Count: 2
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DOI Bookmark: 10.1109/ICCAD.2004.1382556

ABSTRACT

The predictability of memory access patterns in embedded systems can be successfully exploited to devise effective application-specific cache optimizations. In this work, we propose an improved indexing scheme for direct-mapped caches, which drastically reduces the number of conflict misses by using application-specific information; the scheme is based on the selection of a subset of the address bits. With respect to similar approaches, our solution has two main strengths. First, it models the misses analytically by building a miss equation, and exploits a symbolic algorithm to compute the exact optimum solution (i.e., the subset of address bits to be used as cache index that minimizes conflict misses). Second, we designed a re-configurable bit selector, which can be programmed at run-time to fit the optimal cache indexing to a given application. Results show an average reduction of conflict misses of 24%, measured over a set of standard benchmarks, and for different cache configurations.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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[1] A. Macil, L. Benini, M. Poncino, Memory Design Techniques for Low-Energy Embedded Systems, Kluwer Academic Publishers, 2002.
 
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[2] W. Wolf, M. Kandemir, "Memory System Optimization of Embedded Software," Proceedings of the IEEE, Vol. 91, No. 1, pp. 165-182, January 2003.
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[17] M. D. Hill, J. Elder, DineroIV Trace-Driven Uniprocessor Cache Simulator, www.cs.wisc.edu/markhill/DineroIV, 1998.
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[19] T. Givargis, F. Vahid, "Platune: A Tuning Framework for System-on-a-Chip Platforms," IEEE Transactions on Computer Aided Design, Vol. 21, No. 11, Nov. 2002.
 
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[20] New Mexico State University TraceBase, tracebase.nmsu.edu.

Collaborative Colleagues:
K. Patel: colleagues
E. Macii: colleagues
L. Benini: colleagues
M. Poncino: colleagues