| APT: an area-performance-testability driven placement algorithm |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 29th ACM/IEEE Design Automation Conference
table of contents
Anaheim, California, United States
Pages: 141 - 146
Year of Publication: 1992
ISBN:0-89791-516-X
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Authors
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S. Kim
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Center for Reliable and High-Performance Computing, Coordinated Science Laboratory, University of Illinois, Urbana, IL
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P. Banerjee
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Center for Reliable and High-Performance Computing, Coordinated Science Laboratory, University of Illinois, Urbana, IL
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V. Chickermane
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Center for Reliable and High-Performance Computing, Coordinated Science Laboratory, University of Illinois, Urbana, IL
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J. H. Patel
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Center for Reliable and High-Performance Computing, Coordinated Science Laboratory, University of Illinois, Urbana, IL
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IEEE Computer Society Press
Los Alamitos, CA, USA
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| Bibliometrics |
Downloads (6 Weeks): 7, Downloads (12 Months): 8, Citation Count: 1
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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A. E. Dunlop , V. D. Agrawal , D. N. Deutsch , M. F. Jukl , P. Kozak , M. Wiesel, Chip layout optimization using critical path weighting, Proceedings of the 21st conference on Design automation, p.133-136, June 25-27, 1984, Albuquerque, New Mexico, United States
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M. Marek-Sadowska and S. P. Lin, "Timing driven placement," Proc. of Int. Conf. on Computer-aided Design, pp. 94-97, 1989.
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P.S. Hauge, R. Nair, and E. J. Yoffa, "Circuit placement for predictable performance," Proc. of International Conf. on Computer Aided Design, pp. 88-91, 1987.
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Shen Lin , M. Marek-Sadowska , Ernest S. Kuh, Delay and area optimization in standard-cell design, Proceedings of the 27th ACM/IEEE conference on Design automation, p.349-352, June 24-27, 1990, Orlando, Florida, United States
[doi> 10.1145/123186.123301]
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C. Sechen and et al., The TimberWolfSC Distribution 5.4. Yale University, July, 1989.
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V. Chickermane and J. H. Patel, "An optimization based approach to the partial scan design problem," Proc. International Test Conference, pp. 377-386, September, 1990.
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W.C. Elmore, "The transient response of damped linear networks with particular regard to wideband amplifiers," J. Appl. Phys., vol. 19, pp. 55-63, Jan. 1948.
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P. Penfield, Jr., J. Rubinstein, and M. A. Horowitz, "Signal Delay in RC Tree Networks," IEEE Trans. Computer Aided Design, vol. CAD-2, no. 3, pp. 202-211, July 1983.
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13
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K.T. Cheng and V. D. Agrawal, "An economical scan design for sequential logic test generation," Proc. 19th Int'l. Syrup. on Fault-Tolerant Computing, pp. 28-35, 1989.
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R.L. Spickelmier et al, Octtools Distribution 3.0. Electronics Research Lab, UC Berkeley, August, 1989.
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