Niagara: A 32-Way Multithreaded Sparc Processor

ABSTRACT

The Niagara processor implements a thread-rich architecture designed to provide a high-performance solution for commercial server applications. The hardware supports 32 threads with a memory subsystem consisting of an on-board crossbar, level-2 cache, and memory controllers for a highly integrated design that exploits the thread-level parallelism inherent to server applications, while targeting low levels of power consumption.

REFERENCES

• 1: S.R. Kunkel, et al., "A Performance Methodology for Commercial Servers," <i>IBM J. Research and Development,</i> vol. 44, no. 6, 2000, pp. 851-872.
• 2: Luiz André Barroso , Jeffrey Dean , Urs Hölzle, Web Search for a Planet: The Google Cluster Architecture, IEEE Micro, v.23 n.2, p.22-28, March 2003 [doi>10.1109/MM.2003.1196112]
• 3: Kunle Olukotun , Basem A. Nayfeh , Lance Hammond , Ken Wilson , Kunyung Chang, The case for a single-chip multiprocessor, Proceedings of the seventh international conference on Architectural support for programming languages and operating systems, p.2-11, October 01-04, 1996, Cambridge, Massachusetts, United States
• 4: James Laudon , Anoop Gupta , Mark Horowitz, Interleaving: a multithreading technique targeting multiprocessors and workstations, Proceedings of the sixth international conference on Architectural support for programming languages and operating systems, p.308-318, October 05-07, 1994, San Jose, California, United States
• 5: Luiz André Barroso , Kourosh Gharachorloo , Robert McNamara , Andreas Nowatzyk , Shaz Qadeer , Barton Sano , Scott Smith , Robert Stets , Ben Verghese, Piranha: a scalable architecture based on single-chip multiprocessing, Proceedings of the 27th annual international symposium on Computer architecture, p.282-293, June 2000, Vancouver, British Columbia, Canada
• 6: S. Kapil H. McGhan and J. Lawrendra, "A Chip Multithreaded Processor for Network-Facing Workloads," <i>IEEE Micro,</i> vol. 24, no. 2, Mar.-Apr. 2004, pp. 20-30.
• 7: J. Hart, et al., "Implementation of a 4th-Generation 1.8 GHz Dual Core Sparc V9 Microprocessor," <i>Proc. Int'l Solid-State Circuits Conf.</i> (ISSCC 05), IEEE Press, 2005, http://www.isscc.org/isscc/2005/ap/ISSCC2005AdvanceProgram.pdf.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Multiple-instruction-stream, multiple-data-stream processors (MIMD)

Additional Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.2 Design Styles
          Subjects: Shared memory

General Terms:
Design, Experimentation

Keywords:
Microprocessors and microcomputers, Shared memory, Multithreaded processors