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Feedback driven instruction-set extension
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Language, Compiler and Tool Support for Embedded Systems archive
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems table of contents
Washington, DC, USA
SESSION: Caches and instructions sets table of contents
Pages: 126 - 135  
Year of Publication: 2004
ISBN:1-58113-806-7
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Authors
Uwe Kastens  University of Paderborn
Dinh Khoi Le  University of Paderborn
Adrian Slowik  University of Paderborn
Michael Thies  University of Paderborn
Sponsors
ACM: Association for Computing Machinery
SIGBED: ACM Special Interest Group on Embedded Systems
SIGPLAN: ACM Special Interest Group on Programming Languages
Publisher
ACM  New York, NY, USA
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ABSTRACT

Application specific instruction-set processors combine an efficient general purpose core with special purpose functionality that is tailored to a particular application domain. Since the extension of an instruction set and its utilization are non-trivial tasks, sophisticated tools have to provide guidance and support during design. Feedback driven optimization allows for the highest level of specialization, but calls for a simulator that is aware of the newly proposed instructions, a compiler that makes use of these instructions without manual intervention, and an application program that is representative for the targeted application domain.In this paper we introduce an approach for the extension of instruction sets that is built around a concise yet powerful processor abstraction. The specification of a processor is well suited to automatically generate the important parts of a compiler backend and cycle-accurate simulator. A typical design cycle involves the execution of the representative application program, evaluation of performance statistics collected by the simulator, refinement of the processor specification guided by performance statistics, and update of the compiler and simulator according to the refined specification. We demonstrate the usefulness of our novel approach by example of an instruction set for symmetric ciphers.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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L. Pozzi, M. Vuletic, and P. Ienne. Automatic topology-based identification of instruction-set extensions for embedded processors. Technical report, Swiss Federal Institute of Technology Lausanne, Processor Architecture Laboratory, 2001.
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E. Stümpel, M. Thies, and U. Kastens. VLIW compilation techniques for superscalar architectures.
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Collaborative Colleagues:
Uwe Kastens: colleagues
Dinh Khoi Le: colleagues
Adrian Slowik: colleagues
Michael Thies: colleagues