Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining

ABSTRACT

With deep-sub-micron (DSM) technology, statistical timing analysis becomes increasingly crucial to characterize signal transmission over global interconnect wires. In this paper, a novel statistical timing analysis approach has been developed to analyze the behavior of two important pipelined architectures for multiple clock-cycle global interconnect, namely, the flip-flop inserted global wire and the latch inserted global wire. We present analytical formula that is based on parameters obtained using Monte Carlo simulation. These results enable a global interconnect designer to explore design trade-offs between clock frequency and probability of bit-error during data transmission.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability

General Terms:
Algorithms, Design, Performance, Reliability

Keywords:
interconnect pipelining, statistical timing analysis