|
ABSTRACT
Thermal design in sub-100nm technologies is one of the major challenges to the CAD community. In this paper, we first introduce the idea of temperature-aware design. We then propose a compact thermal model which can be integrated with modern CAD tools to achieve a temperature-aware design methodology. Finally, we use the compact thermal model in a case study of microprocessor design to show the importance of using temperature as a guideline for the design. Results from our thermal model show that a temperature-aware design approach can provide more accurate estimations, and therefore better decisions and faster design convergence.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
The international technology roadmap for semiconductors (ITRS), 2003.
|
| |
2
|
K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proceedings of the IEEE, 91(2):305--327, February 2003.
|
| |
3
|
T. Kam, S. Rawat, D. Kirkpatrick, R. Roy, G. S. Spirakis, N. Sherwani, and C. Peterson. EDA challenges facing future microprocessor design. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 19(12):1498--1506, December 2000.
|
| |
4
|
K. Torki and F. Ciontu. IC thermal map from digital and thermal simulations. In Proc. 8th THERMINIC, pages 303--08, Oct. 2002.
|
 |
5
|
Kevin Skadron , Mircea R. Stan , Wei Huang , Sivakumar Velusamy , Karthik Sankaranarayanan , David Tarjan, Temperature-aware microarchitecture, Proceedings of the 30th annual international symposium on Computer architecture, June 09-11, 2003, San Diego, California
|
 |
6
|
Kevin Skadron , Mircea R. Stan , Karthik Sankaranarayanan , Wei Huang , Sivakumar Velusamy , David Tarjan, Temperature-aware microarchitecture: Modeling and implementation, ACM Transactions on Architecture and Code Optimization (TACO), v.1 n.1, p.94-125, March 2004
[doi> 10.1145/980152.980157]
|
| |
7
|
T-Y. Wang and C. C-P. Chen. 3-D thermal-ADI: A linear-time chip level transient thermal simulator. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 21(12):1434--1445, December 2002.
|
| |
8
|
C. J. M. Lasance. Two benchmarks to facilitate the study of compact thermal modeling phenomena. Components and Packaging Technologies, IEEE Transactions on, 24(4):559--565, December 2001.
|
| |
9
|
W. Batty et al. Global coupled EM-electrical-thermal simulation and experimental validation for a spatial power combining MMIC array. Microwave Theory and Techniques, IEEE Transactions on, pages 2820--33, Dec. 2002.
|
| |
10
|
J. Parry, H. Rosten, and G. B. Kromann. The development of component-level thermal compact models of a C4/CBGA interconnect technology: The motorola PowerPC 603 and PowerPC 604 RISC microproceesors. Components, Packaging, and Manufacturing Technology--Part A, IEEE Transactions on, 21(1):104--112, March 1998.
|
| |
11
|
S. Lee, S. Song, V. Au, and K. Moran. Constricting/spreading resistance model for electronics packaging. In Proc. AJTEC, pages 199--206, March 1995.
|
| |
12
|
H. B. Bakoglu. Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley Publishing Company, Reading, Massachusetts, 1990.
|
| |
13
|
W. Huang, M. R. Stan, K. Skadron, K. Sankaranarayanan, S. Ghosh, and S. Velusamy. Compact thermal modeling for temperature-aware design. Tech Report CS-2004-13, Univ. of Virginia Dept. of Computer Science, April. 2004.
|
| |
14
|
J. A. Davis, V. K. De, and J. D. Meindl. A stochastic wire-length distribution for gigascale integration (GSI)--part I: Derivation and validation. Electron Devices, IEEE Transactions on, 45(3):580--589, March 1998.
|
 |
15
|
|
| |
16
|
V. Székely, C. Márta, M. Renze, G. Végh, Z. Benedek, and S. Török. A thermal benchmark chip: Design and applications. Components, Packaging, and Manufacturing Technology--Part A, IEEE Transactions on, 21(3):399--405, September 1998.
|
| |
17
|
S. Rzepka, K. Banerjee, E. Meusel, and C. Hu. Characterization of self-heating in advanced VLSI interconnect lines based on thermal finite element simulation. Components, Packaging, and Manufacturing Technology--Part A, IEEE Transactions on, 21(3):406--411, September 1998.
|
| |
18
|
K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat. 3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. Proceedings of the IEEE, 89(5):602--633, May 2001.
|
 |
19
|
|
| |
20
|
Y.-F. Tsai. An Architecture-Level Leakage Power Simulator. Ph.D. Forum at DATE 2004, Feb. 2004.
|
CITED BY 43
|
|
Aditya Bansal , Mesut Meterelliyoz , Siddharth Singh , Jung Hwan Choi , Jayathi Murthy , Kaushik Roy, Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
|
|
|
Yingmin Li , Mark Hempstead , Patrick Mauro , David Brooks , Zhigang Hu , Kevin Skadron, Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
|
|
|
|
|
|
Wei Huang , Eric Humenay , Kevin Skadron , Mircea R. Stan, The need for a full-chip and package thermal model for thermally optimized IC designs, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
|
|
|
|
|
|
|
|
|
Yen-Wei Wu , Chia-Lin Yang , Ping-Hung Yuh , Yao-Wen Chang, Joint exploration of architectural and physical design spaces with thermal consideration, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Ravishankar Rao , Sarma Vrudhula , Chaitali Chakrabarti , Naehyuck Chang, An optimal analytical solution for processor speed control with thermal constraints, Proceedings of the 2006 international symposium on Low power electronics and design, October 04-06, 2006, Tegernsee, Bavaria, Germany
|
|
|
Taeho Kgil , Shaun D'Souza , Ali Saidi , Nathan Binkert , Ronald Dreslinski , Trevor Mudge , Steven Reinhardt , Krisztian Flautner, PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor, ACM SIGPLAN Notices, v.41 n.11, November 2006
|
|
|
|
|
|
|
|
|
Ja Chun Ku , Serkan Ozdemir , Gokhan Memik , Yehea Ismail, Power density minimization for highly-associative caches in embedded processors, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
|
|
|
Feng Wang , Yuan Xie , N. Vijaykrishnan , M. J. Irwin, On-chip bus thermal analysis and optimization, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
|
|
|
Ayse K. Coskun , Tajana Simunic Rosing , Yusuf Leblebici , Giovanni De Micheli, A simulation methodology for reliability analysis in multi-core SoCs, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
J. M. Wang , B. Srinivas , Dongsheng Ma , C. C. -P. Chen , Jun Li, System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS), Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.728-735, November 06-10, 2005, San Jose, CA
|
|
|
|
|
|
Pu Liu , Zhenyu Qi , Hang Li , Lingling Jin , Wei Wu , S. X. -D. Tan , Jun Yang, Fast thermal simulation for architecture level dynamic thermal management, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.639-644, November 06-10, 2005, San Jose, CA
|
|
|
|
|
|
|
|
|
Pu Liu , Sheldon X.-D. Tan , Wei Wu , Murli Tirumala, FEKIS: a fast architecture-level thermal analyzer for online thermal regulation, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Taeho Kgil , Ali Saidi , Nathan Binkert , Steve Reinhardt , Krisztian Flautner , Trevor Mudge, PicoServer: Using 3D stacking technology to build energy efficient servers, ACM Journal on Emerging Technologies in Computing Systems (JETC), v.4 n.4, p.1-34, October 2008
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|