ACM Home Page
Please provide us with feedback. Feedback
Compact thermal modeling for temperature-aware design
Full text PdfPdf (342 KB)
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 41st annual Design Automation Conference table of contents
San Diego, CA, USA
SESSION: Energy and thermal-aware design table of contents
Pages: 878 - 883  
Year of Publication: 2004
ISBN:1-58113-828-8
Authors
Wei Huang  University of Virginia, Charlottesville, VA
Mircea R. Stan  University of Virginia, Charlottesville, VA
Kevin Skadron  University of Virginia, Charlottesville, VA
Karthik Sankaranarayanan  University of Virginia, Charlottesville, VA
Shougata Ghosh  University of Virginia, Charlottesville, VA
Sivakumar Velusam  University of Virginia, Charlottesville, VA
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 27,   Downloads (12 Months): 152,   Citation Count: 43
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/996566.996800
What is a DOI?

ABSTRACT

Thermal design in sub-100nm technologies is one of the major challenges to the CAD community. In this paper, we first introduce the idea of temperature-aware design. We then propose a compact thermal model which can be integrated with modern CAD tools to achieve a temperature-aware design methodology. Finally, we use the compact thermal model in a case study of microprocessor design to show the importance of using temperature as a guideline for the design. Results from our thermal model show that a temperature-aware design approach can provide more accurate estimations, and therefore better decisions and faster design convergence.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
The international technology roadmap for semiconductors (ITRS), 2003.
 
2
K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proceedings of the IEEE, 91(2):305--327, February 2003.
 
3
T. Kam, S. Rawat, D. Kirkpatrick, R. Roy, G. S. Spirakis, N. Sherwani, and C. Peterson. EDA challenges facing future microprocessor design. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 19(12):1498--1506, December 2000.
 
4
K. Torki and F. Ciontu. IC thermal map from digital and thermal simulations. In Proc. 8th THERMINIC, pages 303--08, Oct. 2002.
5
6
 
7
T-Y. Wang and C. C-P. Chen. 3-D thermal-ADI: A linear-time chip level transient thermal simulator. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 21(12):1434--1445, December 2002.
 
8
C. J. M. Lasance. Two benchmarks to facilitate the study of compact thermal modeling phenomena. Components and Packaging Technologies, IEEE Transactions on, 24(4):559--565, December 2001.
 
9
W. Batty et al. Global coupled EM-electrical-thermal simulation and experimental validation for a spatial power combining MMIC array. Microwave Theory and Techniques, IEEE Transactions on, pages 2820--33, Dec. 2002.
 
10
J. Parry, H. Rosten, and G. B. Kromann. The development of component-level thermal compact models of a C4/CBGA interconnect technology: The motorola PowerPC 603 and PowerPC 604 RISC microproceesors. Components, Packaging, and Manufacturing Technology--Part A, IEEE Transactions on, 21(1):104--112, March 1998.
 
11
S. Lee, S. Song, V. Au, and K. Moran. Constricting/spreading resistance model for electronics packaging. In Proc. AJTEC, pages 199--206, March 1995.
 
12
H. B. Bakoglu. Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley Publishing Company, Reading, Massachusetts, 1990.
 
13
W. Huang, M. R. Stan, K. Skadron, K. Sankaranarayanan, S. Ghosh, and S. Velusamy. Compact thermal modeling for temperature-aware design. Tech Report CS-2004-13, Univ. of Virginia Dept. of Computer Science, April. 2004.
 
14
J. A. Davis, V. K. De, and J. D. Meindl. A stochastic wire-length distribution for gigascale integration (GSI)--part I: Derivation and validation. Electron Devices, IEEE Transactions on, 45(3):580--589, March 1998.
15
 
16
V. Székely, C. Márta, M. Renze, G. Végh, Z. Benedek, and S. Török. A thermal benchmark chip: Design and applications. Components, Packaging, and Manufacturing Technology--Part A, IEEE Transactions on, 21(3):399--405, September 1998.
 
17
S. Rzepka, K. Banerjee, E. Meusel, and C. Hu. Characterization of self-heating in advanced VLSI interconnect lines based on thermal finite element simulation. Components, Packaging, and Manufacturing Technology--Part A, IEEE Transactions on, 21(3):406--411, September 1998.
 
18
K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat. 3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. Proceedings of the IEEE, 89(5):602--633, May 2001.
19
 
20
Y.-F. Tsai. An Architecture-Level Leakage Power Simulator. Ph.D. Forum at DATE 2004, Feb. 2004.

CITED BY  43

Collaborative Colleagues:
Wei Huang: colleagues
Mircea R. Stan: colleagues
Kevin Skadron: colleagues
Karthik Sankaranarayanan: colleagues
Shougata Ghosh: colleagues
Sivakumar Velusam: colleagues