ACM Home Page
Please provide us with feedback. Feedback
Theoretical and practical limits of dynamic voltage scaling
Full text PdfPdf (223 KB)
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 41st annual Design Automation Conference table of contents
San Diego, CA, USA
SESSION: Energy and thermal-aware design table of contents
Pages: 868 - 873  
Year of Publication: 2004
ISBN:1-58113-828-8
Authors
Bo Zhai  University of Michigan, Ann Arbor, MI
David Blaauw  University of Michigan, Ann Arbor, MI
Dennis Sylvester  University of Michigan, Ann Arbor, MI
Krisztian Flautner  ARM Ltd., Cambridge, UK
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 19,   Downloads (12 Months): 128,   Citation Count: 23
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/996566.996798
What is a DOI?

ABSTRACT

Dynamic voltage scaling (DVS) is a popular approach for energy reduction of integrated circuits. Current processors that use DVS typically have an operating voltage range from full to half of the maximum Vdd. However, it is possible to construct designs that operate over a much larger voltage range: from full Vdd to subthreshold voltages. This possibility raises the question of whether a larger voltage range improves the energy efficiency of DVS. First, from a theoretical point of view, we show that for subthreshold supply voltages leakage energy becomes dominant, making "just in time completion" energy inefficient. We derive an analytical model for the minimum energy optimal voltage and study its trends with technology scaling. Second, we use the proposed model to study the workload activity of an actual processor and analyze the energy efficiency as a function of the lower limit of voltage scaling. Based on this study, we show that extending the voltage range below 1/2 Vdd will improve the energy efficiency for most processor designs, while extending this range to subthreshold operation is beneficial only for very specific applications. Finally, we show that operation deep in the subthreshold voltage range is never energy-efficient.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Transmeta Crusoe. http://www.transmeta.com/
 
2
Intel XScale. http://www.intel.com/design/intelxscale/
 
3
IBM PowerPC. http://www.chips.ibm.com/products/powerpc/
4
 
5
T. Sakurai and A. Newton, "Alpha-Power Law MOSFET Model and Its Applications to CMOS Inverter Delay and other Formulas", IEEE JSSCC, Vol. 25, No. 2, April 1990.
 
6
M. Miyazaki, J. Kao, A. Chandrakasan, "A 175mV Multiply-Accumulate Unit using an Adaptive Supply Voltage and Body Bias (ASB) Architecture", ISSCC 2002, pp. 58--59.
 
7
A. Wang, A. Chandrakasan, "A 180mV FFT Processor Using Subthreshold Circuits Techniques", ISSCC 2004, pp. 292--294.
8
 
9
J. D. Meindl and J. A. Davis, "The fundamental limit on binary switching energy for terascale integration (TSI)," IEEE JSSCC, vol. 35, pp. 1515--1516, Oct. 2000.
 
10
F. Møller, "Algorithm and architecture of a 1-V low-power hearing instrument DSP", ISLPED, pp. 711, Aug. 1999
 
11
BSIM3. http://www-device.eecs.berkeley.edu/~bsim3/get.html
12
 
13
14
15
 
16
 
17
 
18
D. Hodges and H. Jackson, Analysis and Design of Digital Integrated Circuits, McGraw-Hill, 1988
 
19
F. Brglez and H. Fujiwara, "A Neutral Netlist of 10 Combinational Circuits and a Target Translator in Fortran", Proc. IEEE ISCAS, pp. 663--698, June 85.
20
 
21
"Power Aware Computing", edited by R. Graybill and R. Melhem, Kluwer Academic/Plenum Publishers, May 2002

CITED BY  23

Collaborative Colleagues:
Bo Zhai: colleagues
David Blaauw: colleagues
Dennis Sylvester: colleagues
Krisztian Flautner: colleagues