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ABSTRACT
Dynamic voltage scaling (DVS) is a popular approach for energy reduction of integrated circuits. Current processors that use DVS typically have an operating voltage range from full to half of the maximum Vdd. However, it is possible to construct designs that operate over a much larger voltage range: from full Vdd to subthreshold voltages. This possibility raises the question of whether a larger voltage range improves the energy efficiency of DVS. First, from a theoretical point of view, we show that for subthreshold supply voltages leakage energy becomes dominant, making "just in time completion" energy inefficient. We derive an analytical model for the minimum energy optimal voltage and study its trends with technology scaling. Second, we use the proposed model to study the workload activity of an actual processor and analyze the energy efficiency as a function of the lower limit of voltage scaling. Based on this study, we show that extending the voltage range below 1/2 Vdd will improve the energy efficiency for most processor designs, while extending this range to subthreshold operation is beneficial only for very specific applications. Finally, we show that operation deep in the subthreshold voltage range is never energy-efficient.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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1
|
Transmeta Crusoe. http://www.transmeta.com/
|
| |
2
|
Intel XScale. http://www.intel.com/design/intelxscale/
|
| |
3
|
IBM PowerPC. http://www.chips.ibm.com/products/powerpc/
|
 |
4
|
|
| |
5
|
T. Sakurai and A. Newton, "Alpha-Power Law MOSFET Model and Its Applications to CMOS Inverter Delay and other Formulas", IEEE JSSCC, Vol. 25, No. 2, April 1990.
|
| |
6
|
M. Miyazaki, J. Kao, A. Chandrakasan, "A 175mV Multiply-Accumulate Unit using an Adaptive Supply Voltage and Body Bias (ASB) Architecture", ISSCC 2002, pp. 58--59.
|
| |
7
|
A. Wang, A. Chandrakasan, "A 180mV FFT Processor Using Subthreshold Circuits Techniques", ISSCC 2004, pp. 292--294.
|
 |
8
|
|
| |
9
|
J. D. Meindl and J. A. Davis, "The fundamental limit on binary switching energy for terascale integration (TSI)," IEEE JSSCC, vol. 35, pp. 1515--1516, Oct. 2000.
|
| |
10
|
F. Møller, "Algorithm and architecture of a 1-V low-power hearing instrument DSP", ISLPED, pp. 711, Aug. 1999
|
| |
11
|
BSIM3. http://www-device.eecs.berkeley.edu/~bsim3/get.html
|
 |
12
|
|
| |
13
|
|
 |
14
|
|
 |
15
|
|
| |
16
|
|
| |
17
|
|
| |
18
|
D. Hodges and H. Jackson, Analysis and Design of Digital Integrated Circuits, McGraw-Hill, 1988
|
| |
19
|
F. Brglez and H. Fujiwara, "A Neutral Netlist of 10 Combinational Circuits and a Target Translator in Fortran", Proc. IEEE ISCAS, pp. 663--698, June 85.
|
 |
20
|
|
| |
21
|
"Power Aware Computing", edited by R. Graybill and R. Melhem, Kluwer Academic/Plenum Publishers, May 2002
|
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|
|
|
|
|
|
|
|
Bo Zhai , Scott Hanson , David Blaauw , Dennis Sylvester, Analysis and mitigation of variability in subthreshold design, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
|
|
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Leyla Nazhandali , Michael Minuth , Bo Zhai , Javin Olson , Todd Austin , David Blaauw, A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution, Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems, September 24-27, 2005, San Francisco, California, USA
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|
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Gregory K. Chen , David Blaauw , Trevor Mudge , Dennis Sylvester , Nam Sung Kim, Yield-driven near-threshold SRAM design, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
|
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|
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|
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Scott Hanson , Bo Zhai , David Blaauw , Dennis Sylvester , Andres Bryant , Xinlin Wang, Energy optimality and variability in subthreshold design, Proceedings of the 2006 international symposium on Low power electronics and design, October 04-06, 2006, Tegernsee, Bavaria, Germany
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|
|
|
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|
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Leyla Nazhandali , Bo Zhai , Javin Olson , Anna Reeves , Michael Minuth , Ryan Helfand , Sanjay Pant , Todd Austin , David Blaauw, Energy Optimization of Subthreshold-Voltage Sensor Network Processors, ACM SIGARCH Computer Architecture News, v.33 n.2, p.197-207, May 2005
|
|
|
Shengqi Yang , Wayne Wolf , N. Vijaykrishnan , D. N. Serpanos , Yuan Xie, Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach, Proceedings of the conference on Design, Automation and Test in Europe, p.64-69, March 07-11, 2005
|
|
|
|
|
|
Sergiu Nedevschi , Lucian Popa , Gianluca Iannaccone , Sylvia Ratnasamy , David Wetherall, Reducing network energy consumption via sleeping and rate-adaptation, Proceedings of the 5th USENIX Symposium on Networked Systems Design and Implementation, p.323-336, April 16-18, 2008, San Francisco, California
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|
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|
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Bo Zhai , Ronald G. Dreslinski , David Blaauw , Trevor Mudge , Dennis Sylvester, Energy efficient near-threshold chip multi-processing, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA
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|
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|
|
|
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Shengqi Yang , Wenping Wang , Tiehan Lu , Wayne Wolf , N. Vijaykrishnan , Yuan Xie, Case study of reliability-aware and low-power design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.7, p.861-873, July 2008
|
|
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Michael B. Henry , Syed I. Haider , Leyla Nazhandali, A low-power parallel design of discrete wavelet transform using subthreshold voltage technology, Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems, October 19-24, 2008, Atlanta, GA, USA
|
|
|
|
|
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Ronald G. Dreslinski , Gregory K. Chen , Trevor Mudge , David Blaauw , Dennis Sylvester , Krisztian Flautner, Reconfigurable energy efficient near threshold cache architectures, Proceedings of the 2008 41st IEEE/ACM International Symposium on Microarchitecture, p.459-470, November 08-12, 2008
|
|
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Sergiu Nedevschi , Jaideep Chandrashekar , Junda Liu , Bruce Nordman , Sylvia Ratnasamy , Nina Taft, Skilled in the art of being idle: reducing energy waste in networked systems, Proceedings of the 6th USENIX symposium on Networked systems design and implementation, p.381-394, April 22-24, 2009, Boston, Massachusetts
|
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