Leakage-and crosstalk-aware bus encoding for total power reduction

ABSTRACT

Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC delays. In this paper, we propose a new bus encoding algorithm and circuit scheme for on-chip buses that eliminates capacitive crosstalk while simultaneously reducing total power. We introduce a new buffer design approach with selective use of high threshold voltage transistors and couple this buffer design with a novel bus encoding scheme. The proposed encoding scheme significantly reduces total power by 26% and runtime leakage power by 42% while also eliminating capacitive crosstalk. In addition, the proposed encoding is specifically optimized to reduce the complexity of the encoding logic, allowing for a significant reduction in overhead which has not been considered in previous bus encoding work.

REFERENCES

• 1: Shekhar Borkar, Design Challenges of Technology Scaling, IEEE Micro, v.19 n.4, p.23-29, July 1999 [doi>10.1109/40.782564]
• 2: James Kao , Siva Narendra , Anantha Chandrakasan, Subthreshold leakage modeling and reduction techniques, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.141-148, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774593]
• 3: Kerry Bernstein , Ching-Te Chuang , Rajiv Joshi , Ruchir Puri, Design and CAD Challenges in sub-90nm CMOS Technologies, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.129, November 09-13, 2003 [doi>10.1109/ICCAD.2003.54]
• 4: Prashant Saxena , Noel Menezes , Pasquale Cocchini , Desmond A. Kirkpatrick, The scaling challenge: can correct-by-construction design help?, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA [doi>10.1145/640000.640014]
• 5: Bret Victor , Kurt Keutzer, Bus encoding to prevent crosstalk delay, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
• 6: Chun-Gi Lyuh, Taewhan Kim. "Low power bus encoding with crosstalk delay elimination," ASIC/SOC Conference, 2002.
• 7: Youngsoo Shin , Takayasu Sakurai, Coupling-driven bus design for low-power application-specific systems, Proceedings of the 38th conference on Design automation, p.750-753, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379059]
• 8: Naehyuck Chang , Kwanho Kim , Jinsung Cho, Bus encoding for low-power high-performance memory systems, Proceedings of the 37th conference on Design automation, p.800-805, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337778]
• 9: S. Tyagi, et al. "A 130nm generation logic technology featuring 70nm transistors, dual-Vt transistors and 6 layers of Cu interconnects," Proc. IEDM, Dec. 2000.
• 10: Dennis Sylvester , Himanshu Kaul, Future performance challenges in nanometer design, Proceedings of the 38th conference on Design automation, p.3-8, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.378245]
• 11: Qi Wang, S.B.K. Vrudhula. "An investigation of power delay trade-offs for dual Vt CMOS circuits," ICCD 1999.
• 12: Navid Azizi , Andreas Moshovos , Farid N. Najm, Low-leakage asymmetric-cell SRAM, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA [doi>10.1145/566408.566422]
• 13: C.K. Cheng, et al, Interconnect Analysis and Synthesis, Wiley and Sons, New York, 2000.
• 14: S. Morton. "Inductance: implications and solutions for high-speed digital circuits - on-chip signaling," ISSCC 2002.
• 15: Kevin M. Lepak , Irwan Luwandi , Lei He, Simultaneous shield insertion and net ordering under explicit RLC noise constraint, Proceedings of the 38th conference on Design automation, p.199-202, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.378463]
• 16: R. Rudell, A. Vincentelli. "Multiple valued minimization for PLA optimization," IEEE CAD, Sep. 1987.
• 17: http://www.specbench.org/osg/cpu2000/CINT2000/. Spec CINT 2000 Benchmarks.
• 18: Lin Li , N. Vijaykrishnan , Mahmut Kandemir , Mary Jane Irwin, Adapative Error Protection for Energy Efficiency, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.2, November 09-13, 2003 [doi>10.1109/ICCAD.2003.25]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Algorithms, Design, Performance

Keywords:
encoding, leakage reduction, low power