The future of multiprocessor systems-on-chips

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The future of multiprocessor systems-on-chips

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 41st annual Design Automation Conference table of contents

San Diego, CA, USA

SESSION: Multiprocessor SoC MPSoC solutions/nightmare table of contents

Pages: 681 - 685

Year of Publication: 2004

ISBN:1-58113-828-8

Author

Wayne Wolf

Princeton University, Princeton, NJ

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 35, Downloads (12 Months): 254, Citation Count: 30

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

This paper surveys the state-of-the-art and pending challenges in MPSoC design. Standards in communications, multimedia, networking, and other areas encourage the development of high-performance platforms that can support a range of implementations of the standard. A multiprocessor system-on-chip includes embedded processors, digital logic, and mixed-signal circuits combined into a heterogeneous multiprocessor. This mix of technologies creates a major challenge for MPSoC design teams. We will look at some existing MPSoC designs and then describe some hardware and software challenges for MPSoC designers.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Intel, "Product Brief: Intel IXP2850 Network Processor," 2002, Available at http://www.intel.com.
	2	Santanu Dutta , Rune Jensen , Alf Rieckmann, Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems, IEEE Design & Test, v.18 n.5, p.21-31, September 2001 [doi>10.1109/54.953269]
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	5	Wayne Wolf and Mahmut Kandemir, "Memory system optimization of embedded software," Proceedings of the IEEE, 91(1), January 2003, pp. 165--182.
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CITED BY 31

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	Guangyu Chen , Feihui Li , Mahmut Kandemir, Compiler-directed channel allocation for saving power in on-chip networks, ACM SIGPLAN Notices, v.41 n.1, p.194-205, January 2006
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	P. Huerta , J. Castillo , J. I. Mártinez , V. López, Multi MicroBlaze system for parallel computing, Proceedings of the 9th International Conference on Circuits, p.1-6, July 11-13, 2005, Athens, Greece
	Arun Kejariwal , Alexander V. Veidenbaum , Alexandru Nicolau , Milind Girkarmark , Xinmin Tian , Hideki Saito, Challenges in exploitation of loop parallelism in embedded applications, Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, October 22-25, 2006, Seoul, Korea
	Minyoung Kim , Sudarshan Banerjee , Nikil Dutt , Nalini Venkatasubramanian, Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies, Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, October 22-25, 2006, Seoul, Korea
	Matteo Monchiero , Gianluca Palermo , Cristina Silvano , Oreste Villa, Power/performance hardware optimization for synchronization intensive applications in MPSoCs, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
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