ACM Home Page
Please provide us with feedback. Feedback
The best of both worlds: the efficient asynchronous implementation of synchronous specifications
Full text PdfPdf (224 KB)
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 41st annual Design Automation Conference table of contents
San Diego, CA, USA
SESSION: Latency tolerance and asynchronous design table of contents
Pages: 588 - 591  
Year of Publication: 2004
ISBN:1-58113-828-8
Authors
Abhijit Davare  University of California, Berkeley, CA
Kelvin Lwin  Cadence Design Systems, San Jose, CA
Alex Kondratyev  Cadence Berkeley Labs, Berkeley, CA
Alberto Sangiovanni-Vincentelli  University of California, Berkeley, CA
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 20,   Citation Count: 0
Additional Information:

abstract   references   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/996566.996727
What is a DOI?

ABSTRACT

The desynchronization approach combines a traditional synchronous specification style with a robust asynchronous implementation model. The main contribution of this paper is the description of two optimizations that decrease the overhead of desynchronization. First, we investigate the use of clustering to vary the granularity of desynchronization. Second, by applying temporal analysis on a formal execution model of the desynchronized design, we uncover significant amounts of timing slack. These methods are successfully applied to industrial RTL designs.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
J. Cortadella, A. Kondratyev, L. Lavagno, C. Sotiriou, "A Concurrent Model for Desynchronization," IWLS 2003.
 
2
J. P. Uyemura, "VLSI clocking and System Design" in Introduction to VLSI Circuits and Systems John Wiley & Sons, 2002.
 
3
 
4
A. Benveniste, L. Carloni, P. Caspi, A. Sangiovanni-Vincentelli. "Heterogeneous Reactive Systems Modeling and Correct-by-Construction Deployment." Proceedings of EmSoft 2003.
 
5
D. Chinnery and K. Keutzer, "Reducing the Timing Overhead," in Closing the Gap between ASIC and Custom: Tools and techniques for High-Performance ASIC design Kluwer Academic Publishers, 2002.
 
6
 
7
T. Murata, "Petri Nets: Properties, analysis and applications," Proceedings of the IEEE, pp. 541--580, Apr. 1989.
8
 
9
 
10
R.M. Cormack, A review of classification (with Discussion). J. Roy. Stat. Soc. A 134:321--367, 1971.

Collaborative Colleagues:
Abhijit Davare: colleagues
Kelvin Lwin: colleagues
Alex Kondratyev: colleagues
Alberto Sangiovanni-Vincentelli: colleagues