Automatic generation of breakpoint hardware for silicon debug

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Automatic generation of breakpoint hardware for silicon debug

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 41st annual Design Automation Conference table of contents

San Diego, CA, USA

SESSION: Advanced test solutions table of contents

Pages: 514 - 517

Year of Publication: 2004

ISBN:1-58113-828-8

Authors

Bart Vermeulen	Philips Research Laboratories, Eindhoven, The Netherlands
Mohammad Z. Urfianto	Royal Institute of Technology, Kista, Sweden
Sandeep K. Goel	Philips Research Laboratories, Eindhoven, The Netherlands

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 11, Downloads (12 Months): 20, Citation Count: 3

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ABSTRACT

Scan-based silicon debug is a technique that can be used to help find design errors in prototype silicon more quickly. One part of this technique involves the inclusion of breakpoint modules during the design stage of the chip. This paper focuses on an innovative approach to automatically generate breakpoint modules by means of a breakpoint description language. This language is illustrated using an example, and experimental results are presented that show the efficiency and effectiveness of this new method for generating breakpoint hardware.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	ARM Limited, http://www.arm.com. ARM920T (Rev1) Technical Reference Manual, 2001.
	2	Hong Hao , Rick Avra, Structured Design-for-Debug - The SuperSPARCTM II Methodology and Implementation, Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test, p.175-183, October 21-25, 1995
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	4	Don Douglas Josephson , Steve Poehhnan , Vincent Govan, Debug methodology for the McKinley processor, Proceedings of the IEEE International Test Conference 2001, p.451-460, October 30-November 01, 2001
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	6	B. Roberts. The verities of verification. Electronic Business, Jan. 2003.
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	8	Bart Vermeulen , Steven Oostdijk , Frank Bouwman, Test and debug strategy of the PNX8525 NexperiaTM digital video platform system chip, Proceedings of the IEEE International Test Conference 2001, p.121-130, October 30-November 01, 2001

CITED BY 3

	Yu-Chin Hsu , Furshing Tsai , Wells Jong , Ying-Tsai Chang, Visibility enhancement for silicon debug, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Ehab Anis , Nicola Nicolici, Interactive presentation: Low cost debug architecture using lossy compression for silicon debug, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Smruti R. Sarangi , Abhishek Tiwari , Josep Torrellas, Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, p.26-37, December 09-13, 2006