Synthesizing interconnect-efficient low density parity check codes

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Synthesizing interconnect-efficient low density parity check codes

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 41st annual Design Automation Conference table of contents

San Diego, CA, USA

SESSION: High-level techniques for signal processing table of contents

Pages: 488 - 491

Year of Publication: 2004

ISBN:1-58113-828-8

Authors

Marghoob Mohiyuddin	The University of Texas at Austin, Austin, TX
Amit Prakash	The University of Texas at Austin, Austin, TX
Adnan Aziz	The University of Texas at Austin, Austin, TX
Wayne Wolf	Princeton University, Princeton, NJ

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 3, Downloads (12 Months): 23, Citation Count: 1

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ABSTRACT

Error correcting codes are widely used in communication and storage applications. Codec complexity has usually been measured with a software implementation in mind. A recent hardware implementation of a Low Density Parity Check code (LDPC) indicates that interconnect complexity dominates the VLSI cost. We describe a heuristic interconnect-aware synthesis algorithm which generates LDPC codes that use an order of magnitude less wiring with little or no loss of coding efficiency.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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