System design for DSP applications in transaction level modeling paradigm

ABSTRACT

In this paper, we systematically define three transaction level models (TLMs), which reside at different levels of abstraction between the functional and the implementation model of a DSP system. We also show a unique language support to build the TLMs. Our results show that the abstract TLMs can be built and simulated much faster than the implementation model at the expense of a reasonable amount of simulation accuracy.

REFERENCES

• 1: James A. Rowson , Alberto Sangiovanni-Vincentelli, Interface-based design, Proceedings of the 34th annual conference on Design automation, p.178-183, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266060]
• 2: Christopher K. Lennard , Patrick Schaumont , Gjalt de Jong , Anssi Haverinen , Pete Hardee, Standards for system-level design: practical reality or solution in search of a question?, Proceedings of the conference on Design, automation and test in Europe, p.576-585, March 27-30, 2000, Paris, France [doi>10.1145/343647.343859]
• 3: Pieter van der Wolf , Paul Lieverse , Mudit Goel , David La Hei , Kees Vissers, An MPEG-2 decoder case study as a driver for a system level design methodology, Proceedings of the seventh international workshop on Hardware/software codesign, p.33-37, March 1999, Rome, Italy [doi>10.1145/301177.301196]
• 4: E. A. de Kock , W. J. M. Smits , P. van der Wolf , J.-Y. Brunel , W. M. Kruijtzer , P. Lieverse , K. A. Vissers , G. Essink, YAPI: application modeling for signal processing systems, Proceedings of the 37th conference on Design automation, p.402-405, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337511]
• 5: Marco Sgroi , Luciano Lavagno , Alberto Sangiovanni-Vincentelli, Formal Models for Embedded System Design, IEEE Design & Test, v.17 n.2, p.14-27, April 2000 [doi>10.1109/54.844330]
• 6: K. Keutzer, S. Malik, A.R. Newton, J.M. Rabaey and A. Sangiovanni-Vincentelli, "System-Level Design: Orthogonalization of Concerns and Platform based Design," IEEE Trans. CAD, vol. 19, pp. 1523--1543, Dec. 2000.
• 7: Thorsten Grotker, System Design with SystemC, Kluwer Academic Publishers, Norwell, MA, 2002
• 8: R. Dömer, D.D. Gajski and A. Gerstlauer, "SpecC Methodology for High-Level Modeling," in Proc. 9th IEEE/DATC Electronic Design Processes Workshop, Monterey, CA, Apr. 2002.
• 9: Lukai Cai , Daniel Gajski, Transaction level modeling: an overview, Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, October 01-03, 2003, Newport Beach, CA, USA [doi>10.1145/944645.944651]
• 10: A. Hemani, Abhijit K. Deb, J. Öberg, A. Postula, D. Lindqvist and B. Fjellborg, "System Level Virtual Prototyping of DSP SOCs Using Grammar Based Approach," Kluwer Design Automation for Embedded Systems, vol. 5, no. 3, pp. 295--311, Aug. 2000.
• 11: Abhijit K. Deb , Axel Jantsch , Johnny Öberg, System Design for DSP Applications Using the MASIC Methodology, Proceedings of the conference on Design, automation and test in Europe, p.10630, February 16-20, 2004
• 12: G. Kahn, "The Semantics of a Simple Language for Parallel Programming," in Proc. IFIP Congress '74, pp. 471--474, Aug. 1974.
• 13: Edward Ashford Lee , David G. Messerschmitt, Static scheduling of synchronous data flow programs for digital signal processing, IEEE Transactions on Computers, v.36 n.1, p.24-35, Jan. 1987 [doi>10.1109/TC.1987.5009446]
• 14: J.T. Buck and E.A. Lee, "Scheduling Dynamic Dataflow Graphs with Bounded Memory Using the Token Flow Model," in Proc. Int. Conf. Acoustics Speech & Signal Processing, pp. 429--432, Apr. 1993.
• 15: A. Seawright, F. Brewer, "Clairvoyant: A Synthesis System for Production-based Specification," IEEE Trans. VLSI, vol. 2 no. 2, pp. 172--185, June 1994.
• 16: Johnny Öberg , Ahmed Hemani , Anshul Kumar, Grammar-based hardware synthesis from port-size independent specifications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.8 n.2, p.184-194, April 2000 [doi>10.1109/92.831438]
• 17: Robert Siegmund , Dietmar Müller, Automatic Synthesis of Communication Controller Hardware from Protocol Specifications, IEEE Design & Test, v.19 n.4, p.84-95, July 2002 [doi>10.1109/MDT.2002.1018137]
• 18: A. Seawright , J. Buck , U. Holtmann , W. Meyer , B. Pangrle , R. Verbrugghe, A system for compiling and debugging structured data processing controllers, Proceedings of the conference on European design automation, p.86-91, September 1996, Geneva, Switzerland
• 19: Alfred V. Aho , Ravi Sethi , Jeffrey D. Ullman, Compilers: principles, techniques, and tools, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1986
• 20: T. Basten and J. Hoogerbrugge, "Efficient Execution of Process Networks," in Proc. Communicating Process Architectures, pp. 1--14, IOS Press, Amsterdam, 2001.
• 21: A Network on Chip Architecture and Design Methodology, Proceedings of the IEEE Computer Society Annual Symposium on VLSI, p.117, April 25-26, 2002
• 22: K. Lahiri, A. Raghunathan and S. Dey, "System-Level Performance Analysis for Designing On-Chip Communication Architectures," IEEE Trans. CAD, vol. 20, no. 6, pp. 768--783, Jun. 2001.
• 23: Roberto Passerone , James A. Rowson , Alberto Sangiovanni-Vincentelli, Automatic synthesis of interfaces between incompatible protocols, Proceedings of the 35th annual conference on Design automation, p.8-13, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277047]
• 24: AMBA on-chip bus specification {Online}, http://www.arm.com
• 25: MIPS32 4K Processor Core Family Integrator's Manual, {Online}, http://www.mips.com.

INDEX TERMS

Primary Classification:
  J. Computer Applications
  J.6 COMPUTER-AIDED ENGINEERING
      Subjects: Computer-aided design (CAD)

Additional Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Signal processing systems; Real-time and embedded systems

General Terms:
Design, Languages

Keywords:
DSP, grammar, system design, transaction level modeling