Novel sizing algorithm for yield improvement under process variation in nanometer technology

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Novel sizing algorithm for yield improvement under process variation in nanometer technology

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 41st annual Design Automation Conference table of contents

San Diego, CA, USA

SESSION: Yield estimation and optimization table of contents

Pages: 454 - 459

Year of Publication: 2004

ISBN:1-58113-828-8

Authors

Seung Hoon Choi	Intel Corporation, Hillsboro, OR
Bipul C. Paul	Purdue University, W. Lafayette, IN
Kaushik Roy	Purdue University, W. Lafayette, IN

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 41, Citation Count: 32

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ABSTRACT

Due to process parameter variations, a large variability in circuit delay occurs in scaled technologies affecting the yield. In this paper, we propose a sizing algorithm to ensure the speed of a circuit under process variation with a certain degree of confidence while maintaining the area and power budget within a limit. This algorithm estimates the variation in circuit delay using statistical timing analysis considering both inter- and intra-die process variation and resizes the circuit to achieve a desired yield. Experimental results on several benchmark circuits show that one can achieve up to 19% savings in area (power) using our algorithm compared to the worst-case design.

REFERENCES

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	Ashish Srivastava , Saumil Shah , Kanak Agarwal , Dennis Sylvester , David Blaauw , Stephen Director, Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
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